mock-array-big: Directional port names

Necessary to connect the correct top-level buses to the elements after cleaning up names there. Also some additional cleanup/clarifications, as it was quite difficult to read before.

Signed-off-by: Jake Taylor <[email protected]>

Author: yupferris

flow/designs/asap7/mock-array-big/io.tcl

@@ -15,23 +15,23 @@ set cols [expr {[info exists ::env(MOCK_ARRAY_WIDTH)] ? $::env(MOCK_ARRAY_WIDTH)
 set assignments [list \
     top \
     [ concat \
-        {*}[pin2 {io_insHorizontal_1_%d[%d]} $cols $data_width] \
-        {*}[pin2 {io_outsHorizontal_1_%d[%d]} $cols $data_width] \
+        {*}[pin2 {io_insDown_%d[%d]} $cols $data_width] \
+        {*}[pin2 {io_outsUp_%d[%d]} $cols $data_width] \
     ] \
     bottom \
     [ concat \
-        {*}[pin2 {io_insHorizontal_0_%d[%d]} $cols $data_width] \
-        {*}[pin2 {io_outsHorizontal_0_%d[%d]} $cols $data_width] \
+        {*}[pin2 {io_insUp_%d[%d]} $cols $data_width] \
+        {*}[pin2 {io_outsDown_%d[%d]} $cols $data_width] \
     ] \
     left \
     [ concat \
-        {*}[pin2 {io_insVertical_1_%d[%d]} $rows $data_width] \
-        {*}[pin2 {io_outsVertical_1_%d[%d]} $rows $data_width] \
+        {*}[pin2 {io_insRight_%d[%d]} $rows $data_width] \
+        {*}[pin2 {io_outsLeft_%d[%d]} $rows $data_width] \
     ] \
     right \
     [ concat \
-        {*}[pin2 {io_insVertical_0_%d[%d]} $rows $data_width] \
-        {*}[pin2 {io_outsVertical_0_%d[%d]} $rows $data_width] \
+        {*}[pin2 {io_insLeft_%d[%d]} $rows $data_width] \
+        {*}[pin2 {io_outsRight_%d[%d]} $rows $data_width] \
     ] \
 ]
 

flow/designs/src/mock-array-big/Element.v

@@ -1,33 +1,33 @@
 module Element(
   input        clock,
-  input  [7:0] io_ins_down, // @[src/test/scala/MockArray.scala 50:9]
-  input  [7:0] io_ins_right, // @[src/test/scala/MockArray.scala 50:9]
-  input  [7:0] io_ins_up, // @[src/test/scala/MockArray.scala 50:9]
-  input  [7:0] io_ins_left, // @[src/test/scala/MockArray.scala 50:9]
-  output [7:0] io_outs_down, // @[src/test/scala/MockArray.scala 50:9]
-  output [7:0] io_outs_right, // @[src/test/scala/MockArray.scala 50:9]
-  output [7:0] io_outs_up, // @[src/test/scala/MockArray.scala 50:9]
-  output [7:0] io_outs_left // @[src/test/scala/MockArray.scala 50:9]
+  input  [7:0] io_ins_down, // @[src/test/scala/MockArray.scala 54:9]
+  input  [7:0] io_ins_right, // @[src/test/scala/MockArray.scala 54:9]
+  input  [7:0] io_ins_up, // @[src/test/scala/MockArray.scala 54:9]
+  input  [7:0] io_ins_left, // @[src/test/scala/MockArray.scala 54:9]
+  output [7:0] io_outs_down, // @[src/test/scala/MockArray.scala 54:9]
+  output [7:0] io_outs_right, // @[src/test/scala/MockArray.scala 54:9]
+  output [7:0] io_outs_up, // @[src/test/scala/MockArray.scala 54:9]
+  output [7:0] io_outs_left // @[src/test/scala/MockArray.scala 54:9]
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
   reg [31:0] _RAND_3;
 `endif // RANDOMIZE_REG_INIT
-  reg [7:0] REG; // @[src/test/scala/MockArray.scala 54:56]
-  reg [7:0] REG_1; // @[src/test/scala/MockArray.scala 54:56]
-  reg [7:0] REG_2; // @[src/test/scala/MockArray.scala 54:56]
-  reg [7:0] REG_3; // @[src/test/scala/MockArray.scala 54:56]
-  assign io_outs_down = REG_3; // @[src/test/scala/MockArray.scala 54:87]
-  assign io_outs_right = REG_2; // @[src/test/scala/MockArray.scala 54:87]
-  assign io_outs_up = REG_1; // @[src/test/scala/MockArray.scala 54:87]
-  assign io_outs_left = REG; // @[src/test/scala/MockArray.scala 54:87]
+  reg [7:0] REG; // @[src/test/scala/MockArray.scala 61:56]
+  reg [7:0] REG_1; // @[src/test/scala/MockArray.scala 61:56]
+  reg [7:0] REG_2; // @[src/test/scala/MockArray.scala 61:56]
+  reg [7:0] REG_3; // @[src/test/scala/MockArray.scala 61:56]
+  assign io_outs_down = REG_3; // @[src/test/scala/MockArray.scala 61:87]
+  assign io_outs_right = REG_2; // @[src/test/scala/MockArray.scala 61:87]
+  assign io_outs_up = REG_1; // @[src/test/scala/MockArray.scala 61:87]
+  assign io_outs_left = REG; // @[src/test/scala/MockArray.scala 61:87]
   always @(posedge clock) begin
-    REG <= io_ins_down; // @[src/test/scala/MockArray.scala 54:56]
-    REG_1 <= io_ins_right; // @[src/test/scala/MockArray.scala 54:56]
-    REG_2 <= io_ins_up; // @[src/test/scala/MockArray.scala 54:56]
-    REG_3 <= io_ins_left; // @[src/test/scala/MockArray.scala 54:56]
+    REG <= io_ins_down; // @[src/test/scala/MockArray.scala 61:56]
+    REG_1 <= io_ins_right; // @[src/test/scala/MockArray.scala 61:56]
+    REG_2 <= io_ins_up; // @[src/test/scala/MockArray.scala 61:56]
+    REG_3 <= io_ins_left; // @[src/test/scala/MockArray.scala 61:56]
   end
 // Register and memory initialization
 `ifdef RANDOMIZE_GARBAGE_ASSIGN