Skip to content

Commit d33aa7a

Browse files
malibertymaliberty
authored
Merge pull request #2895 from jeffng-or/nangate45-mempool_group
Added mempool_group SV in prep for SV enablement
2 parents ada0e14 + c995552 commit d33aa7a

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

62 files changed

+17531
-11
lines changed

‎flow/designs/nangate45/mempool_group/config.mk‎

Lines changed: 61 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,23 +5,73 @@ export PLATFORM = nangate45
55
export SYNTH_HIERARCHICAL = 1
66

77
export TEMP_DESIGN_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)
8-
export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v
8+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_group.sv \
9+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_pkg.sv \
10+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/cf_math_pkg.sv \
11+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv \
12+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi_hier_interco.sv \
13+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_tile.sv \
14+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \
15+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_pkg.sv \
16+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_pkg.sv \
17+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_mux.sv \
18+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_id_remap.sv \
19+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_cc.sv \
20+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache.sv \
21+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tcdm_adapter.sv \
22+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tech_cells_generic/src/rtl/tc_sram.sv \
23+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/spill_register.sv \
24+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/fall_through_register.sv \
25+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_xbar.sv \
26+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/address_scrambler.sv \
27+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tcdm_shim.sv \
28+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_demux.sv \
29+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_axi_adapter.sv \
30+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_cut.sv \
31+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_intf.sv \
32+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/riscv_instr.sv \
33+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_id_prepend.sv \
34+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/rr_arb_tree.sv \
35+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/fifo_v3.sv \
36+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/lzc.sv \
37+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch.sv \
38+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_ipu.sv \
39+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv \
40+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/isochronous_spill_register.sv \
41+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv \
42+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv \
43+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_arbiter.sv \
44+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv \
45+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/onehot_to_bin.sv \
46+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_demux.sv \
47+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/deprecated/fifo_v2.sv \
48+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/spill_register_flushable.sv \
49+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_arbiter_flushable.sv \
50+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/latch_scm.sv \
51+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_lsu.sv \
52+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tech_cells_generic/src/rtl/tc_clk.sv \
53+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv \
54+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch_addr_demux.sv \
55+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_regfile_ff.sv \
56+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_shared_muldiv.sv \
57+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/deprecated/find_first_one.sv \
58+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_onehot.sv \
59+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv
60+
61+
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl \
62+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/register_interface/include
963

1064
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sdc
1165

1266
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x32.lef \
13-
$(PLATFORM_DIR)/lef/fakeram45_64x64.lef \
14-
$(PLATFORM_DIR)/lef/fakeram45_128x32.lef \
15-
$(PLATFORM_DIR)/lef/fakeram45_128x256.lef
67+
$(PLATFORM_DIR)/lef/fakeram45_64x64.lef
1668

1769
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x32.lib \
18-
$(PLATFORM_DIR)/lib/fakeram45_128x32.lib \
19-
$(PLATFORM_DIR)/lib/fakeram45_64x64.lib \
20-
$(PLATFORM_DIR)/lib/fakeram45_128x256.lib
70+
$(PLATFORM_DIR)/lib/fakeram45_64x64.lib
2171

22-
export DIE_AREA = 0 0 4400 4400
23-
export CORE_AREA = 10 12 4390 4390
72+
export DIE_AREA = 0 0 1100 1100
73+
export CORE_AREA = 10 12 1090 1090
2474

25-
export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-1000 -exclude bottom:3400-4400
75+
export MACRO_PLACE_HALO = 10 10
2676

27-
export MACRO_PLACE_HALO = 10 10
77+
export SYNTH_USE_SLANG = 1

‎flow/designs/nangate45/mempool_group/mempool_group.sdc‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
set sdc_version 2.0
2+
set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
3+
4+
set clock_cycle 3
5+
set uncertainty [expr $clock_cycle*0.02]
6+
set io_delay 0
7+
set maxFanout 16
8+
set maxTransition [expr $clock_cycle*0.01]
9+
set pre_cts_clock_latency_estimate 0.070
10+
set clock_port_mempool_tile clk_i
11+
12+
create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
13+
set_clock_uncertainty $uncertainty [all_clocks]
14+
set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
15+
set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
16+
set_max_transition $maxTransition -clock_path [get_clocks clk_i]
17+
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
18+
#set_propagated_clock [get_clocks clk_i]
19+
20+
21+
# Create virtual clock.
22+
create_clock -name "vclk_i" -period $clock_cycle
23+
set_clock_uncertainty $uncertainty [get_clocks vclk_i]
24+
set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
25+
set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
26+
27+
28+
set_case_analysis 0 [get_ports scan_enable_i]
29+
set_max_fanout $maxFanout [current_design]
30+
31+
32+
33+
# False path some of the quasi-static signals.
34+
#set_false_path -from tile_id_i
35+
36+
# TCDM Master
37+
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}]
38+
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_*req_*_o}]
39+
40+
set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}]
41+
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_o}]
42+
43+
# TCDM Slave
44+
#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_i}]
45+
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_o}]
46+
47+
set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}]
48+
set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_o}]
49+
50+
# Refill port
51+
#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_i}]
52+
#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_o}]
53+
54+
# Reset
55+
set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
56+
57+
# Critical range
58+
# Depending on the synthesis tool used, this can be helpful.
59+
#set_critical_range 0.100 [current_design]

‎flow/designs/src/mempool_group/README.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
Extracted from https://github.com/TILOS-AI-Institute/MacroPlacement

‎flow/designs/src/mempool_group/rtl/address_scrambler.sv‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
1+
// Copyright 2021 ETH Zurich and University of Bologna.
2+
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
3+
// SPDX-License-Identifier: SHL-0.51
4+
5+
// Description: Scrambles the address in such a way, that part of the memory is accessed
6+
// sequentially and part is interleaved.
7+
// Current constraints:
8+
9+
// Author: Samuel Riedel <[email protected]>
10+
11+
module address_scrambler #(
12+
parameter int unsigned AddrWidth = 32,
13+
parameter int unsigned ByteOffset = 2,
14+
parameter int unsigned NumTiles = 2,
15+
parameter int unsigned NumBanksPerTile = 2,
16+
parameter bit Bypass = 0,
17+
parameter int unsigned SeqMemSizePerTile = 4*1024
18+
) (
19+
input logic [AddrWidth-1:0] address_i,
20+
output logic [AddrWidth-1:0] address_o
21+
);
22+
localparam int unsigned BankOffsetBits = $clog2(NumBanksPerTile);
23+
localparam int unsigned TileIdBits = $clog2(NumTiles);
24+
localparam int unsigned SeqPerTileBits = $clog2(SeqMemSizePerTile);
25+
localparam int unsigned SeqTotalBits = SeqPerTileBits+TileIdBits;
26+
localparam int unsigned ConstantBitsLSB = ByteOffset + BankOffsetBits;
27+
localparam int unsigned ScrambleBits = SeqPerTileBits-ConstantBitsLSB;
28+
29+
if (Bypass || NumTiles < 2) begin
30+
assign address_o = address_i;
31+
end else begin
32+
logic [ScrambleBits-1:0] scramble; // Address bits that have to be shuffled around
33+
logic [TileIdBits-1:0] tile_id; // Which tile does this address region belong to
34+
35+
// Leave this part of the address unchanged
36+
// The LSBs that correspond to the offset inside a tile. These are the byte offset (bank width)
37+
// and the Bank offset (Number of Banks in tile)
38+
assign address_o[ConstantBitsLSB-1:0] = address_i[ConstantBitsLSB-1:0];
39+
// The MSBs that are outside of the sequential memory size. Currently the sequential memory size
40+
// always starts at 0. These are all the MSBs up to SeqMemSizePerTile*NumTiles
41+
assign address_o[AddrWidth-1:SeqTotalBits] = address_i[AddrWidth-1:SeqTotalBits];
42+
43+
// Scramble the middle part
44+
// Bits that would have gone to different tiles but now go to increasing lines in the same tile
45+
assign scramble = address_i[SeqPerTileBits-1:ConstantBitsLSB]; // Bits that would
46+
// Bits that would have gone to increasing lines in the same tile but now go to different tiles
47+
assign tile_id = address_i[SeqTotalBits-1:SeqPerTileBits];
48+
49+
always_comb begin
50+
// Default: Unscrambled
51+
address_o[SeqTotalBits-1:ConstantBitsLSB] = {tile_id, scramble};
52+
// If not in bypass mode and address is in sequential region and more than one tile
53+
if (address_i < (NumTiles * SeqMemSizePerTile)) begin
54+
address_o[SeqTotalBits-1:ConstantBitsLSB] = {scramble, tile_id};
55+
end
56+
end
57+
end
58+
59+
// Check for unsupported configurations
60+
if (NumBanksPerTile < 2)
61+
$fatal(1, "NumBanksPerTile must be greater than 2. The special case '1' is currently not supported!");
62+
if (SeqMemSizePerTile % (2**ByteOffset*NumBanksPerTile) != 0)
63+
$fatal(1, "SeqMemSizePerTile must be a multiple of BankWidth*NumBanksPerTile!");
64+
endmodule : address_scrambler

0 commit comments

Comments
 (0)