Merge remote-tracking branch 'private/master' into secure-gpl-binSize-float

Author: gudeh

docs/user/FlowVariables.md

@@ -179,9 +179,12 @@ configuration file.
 | <a name="SKIP_REPORT_METRICS"></a>SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| | |
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| | |
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| -flatten| |
+| <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| | |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
+| <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | |
+| <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | |
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| | |
 | <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | |
 | <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | |
@@ -204,13 +207,14 @@ configuration file.
 - [LATCH_MAP_FILE](#LATCH_MAP_FILE)
 - [MAX_UNGROUP_SIZE](#MAX_UNGROUP_SIZE)
 - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS)
-- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER)
-- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER)
 - [SDC_FILE](#SDC_FILE)
 - [SDC_GUT](#SDC_GUT)
+- [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
 - [SYNTH_GUT](#SYNTH_GUT)
 - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
 - [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
+- [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
+- [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
 - [VERILOG_FILES](#VERILOG_FILES)
@@ -246,6 +250,8 @@ configuration file.
 - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
 - [PLACE_SITE](#PLACE_SITE)
 - [REMOVE_ABC_BUFFERS](#REMOVE_ABC_BUFFERS)
+- [RESYNTH_AREA_RECOVER](#RESYNTH_AREA_RECOVER)
+- [RESYNTH_TIMING_RECOVER](#RESYNTH_TIMING_RECOVER)
 - [RTLMP_AREA_WT](#RTLMP_AREA_WT)
 - [RTLMP_ARGS](#RTLMP_ARGS)
 - [RTLMP_BOUNDARY_WT](#RTLMP_BOUNDARY_WT)

flow/BUILD.bazel

@@ -9,7 +9,7 @@ module(
 bazel_dep(name = "bazel-orfs")
 git_override(
     module_name = "bazel-orfs",
-    commit = "f11fbdb35eeae7f8d5e08a58fb7d040f11cb9f04",
+    commit = "4392a87877b4196502fc89dcdf898fd6efdb3fc0",
     remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git",
 )
 
@@ -42,20 +42,17 @@ use_repo(pip, "orfs-pip")
 
 orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories")
 orfs.default(
-    # To build an ORFS image from a PR:
-    # ./build_openroad.sh --latest
+    # Check out the version you want to test and make any modifications locally:
     #
-    # Check out the PRs and modify the local repository as needed
     # ./build_openroad.sh --no_init
     #
-    # docker tag docker.io/openroad/flow-ubuntu22.04-builder:c46d41 gcr.io/ascenium/orfs-megaboom/flow-ubuntu22.04-builder:c46d41
-    # docker push gcr.io/ascenium/orfs-megaboom/flow-ubuntu22.04-builder:c46d41
-    # image = "gcr.io/ascenium/orfs-megaboom/flow-ubuntu22.04-builder:c46d41",
-    #
+    # Comment out "sha256" below, not available for local docker images
+    # and update "image" to point to the local image.
+
     # Official image https://hub.docker.com/r/openroad/orfs/tags
-    image = "docker.io/openroad/orfs:v3.0-2130-g6b38aeeb",
+    image = "docker.io/openroad/orfs:v3.0-2528-ga8780221",
     # image = "gcr.io/ascenium/orfs-megaboom/flow-ubuntu22.04-builder:3d2c3d-2",
-    sha256 = "f5b573d244862bc59f858e2a3586c48aef70989e98f6541099bd15a720e28e7e",
+    sha256 = "5093434a9d3adaaf8e9a4d62fc0df2537d43ceaf01bf2acf9e94d9d38131b7ca",
 )
 use_repo(orfs, "com_github_nixos_patchelf_download")
 use_repo(orfs, "docker_orfs")

flow/MODULE.bazel

@@ -337,7 +337,7 @@ $(DONT_USE_LIBS): $$(filter %$$(@F) %$$(@F).gz,$(LIB_FILES))
 	@mkdir -p $(OBJECTS_DIR)/lib
 	$(UTILS_DIR)/preprocessLib.py -i $^ -o $@
 
-$(OBJECTS_DIR)/lib/merged.lib:
+$(OBJECTS_DIR)/lib/merged.lib: $(DONT_USE_LIBS)
 	$(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@
 
 # Pre-process KLayout tech
@@ -437,19 +437,19 @@ $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
 	mkdir -p $(dir $@)
 	echo $(ABC_CLOCK_PERIOD_IN_PS) > $@
 
-YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(DFF_LIB_FILE) $(VERILOG_FILES) $(CACHED_NETLIST) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
+YOSYS_DEPENDENCIES=$(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)
 
 .PHONY: yosys-dependencies
 yosys-dependencies: $(YOSYS_DEPENDENCIES)
 
 .PHONY: do-yosys
-do-yosys:
+do-yosys: $(DONT_USE_SC_LIB)
 	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR)
 	(export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \
 	$(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys.log)
 
 .PHONY: do-yosys-canonicalize
-do-yosys-canonicalize: yosys-dependencies
+do-yosys-canonicalize: yosys-dependencies $(DONT_USE_SC_LIB)
 	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR)
 	($(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SCRIPTS_DIR)/synth_canonicalize.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_canonicalize.log)
 
@@ -594,7 +594,7 @@ endef
 
 # STEP 1: Translate verilog to odb
 #-------------------------------------------------------------------------------
-$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL),floorplan))
+$(eval $(call do-step,2_1_floorplan,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE) $(FOOTPRINT_TCL) $(DONT_USE_SC_LIB),floorplan))
 
 # STEP 2: Random IO placement
 #-------------------------------------------------------------------------------
@@ -619,7 +619,7 @@ $(eval $(call do-copy,2_floorplan,2_5_floorplan_pdn.odb,))
 $(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.odb
 
 .PHONY: do-floorplan
-do-floorplan:
+do-floorplan: $(DONT_USE_SC_LIB)
 	$(UNSET_AND_MAKE) do-2_1_floorplan do-2_2_floorplan_io do-2_3_floorplan_macro do-2_4_floorplan_tapcell do-2_5_floorplan_pdn do-2_floorplan do-2_floorplan.sdc
 
 .PHONY: clean_floorplan
@@ -1026,6 +1026,11 @@ run:
 	@mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR) $(OBJECTS_DIR)
 	($(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-python) $(RUN_SCRIPT) 2>&1 | tee $(abspath $(LOG_DIR)/$(RUN_LOG_NAME_STEM).log))
 
+export RUN_YOSYS_ARGS ?= -c $(SCRIPTS_DIR)/yosys_keep.tcl
+.phony: run-yosys
+run-yosys:
+	$(YOSYS_EXE) $(RUN_YOSYS_ARGS)
+
 # Utilities
 #-------------------------------------------------------------------------------
 include $(UTILS_DIR)/utils.mk

flow/MODULE.bazel.lock

@@ -24,15 +24,15 @@
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 1087,
+        "value": 1025,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 75547,
+        "value": 71923,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -48,23 +48,23 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -104.94,
+        "value": -86.6,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 7371,
+        "value": 7354,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
         "value": 478,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 399,
+        "value": 326,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -22.74,
+        "value": -21.47,
         "compare": ">="
     }
 }

flow/Makefile

@@ -48,11 +48,11 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -83.87,
+        "value": -68.71,
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 2360,
+        "value": 2359,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
@@ -64,7 +64,7 @@
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -24.19,
+        "value": -21.4,
         "compare": ">="
     }
 }

flow/designs/asap7/aes-block/rules-base.json

@@ -0,0 +1,47 @@
+load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_synth")
+
+BLACKBOXES = [
+    "aes_sbox",
+    "aes_key_expand_128",
+    "aes_cipher_top",
+]
+
+[orfs_synth(
+    name = "{name}_netlist_synth".format(name = name),
+    arguments = {
+        "SDC_FILE": "$(location :constraint.sdc)",
+        "SYNTH_BLACKBOXES": " ".join([b for b in BLACKBOXES if b != name]),
+    },
+    data = [":constraint.sdc"],
+    module_top = name,
+    variant = "netlist",
+    verilog_files = ["//designs/src/aes:verilog"],
+) for name in BLACKBOXES]
+
+[filegroup(
+    name = "{name}_netlist".format(name = name),
+    srcs = ["{name}_netlist_synth".format(name = name)],
+    output_group = "1_synth.v",
+) for name in BLACKBOXES]
+
+filegroup(
+    name = "netlists",
+    srcs = [":{}_netlist".format(name) for name in BLACKBOXES],
+)
+
+orfs_flow(
+    name = "aes_cipher_top",
+    arguments = {
+        "ABC_AREA": "1",
+        "CORE_UTILIZATION": "40",
+        "CORE_ASPECT_RATIO": "1",
+        "CORE_MARGIN": "2",
+        "PLACE_DENSITY": "0.65",
+        "TNS_END_PERCENT": "100",
+    },
+    sources = {
+        "SDC_FILE": [":constraint.sdc"],
+        "SYNTH_NETLIST_FILES": [":netlists"],
+    },
+    top = "aes_cipher_top",
+)

flow/designs/asap7/aes-mbff/rules-base.json

@@ -0,0 +1,28 @@
+# Parallel synthesis with SYNTH_BLACKBOXES
+
+For large designs, it can be useful to split synthesis for the
+major blocks and combine the synthesized result.
+
+SYNTH_HIERARCHICAL=1 and MAX_UNGROUP_SIZE can be used to adjust which
+modules are flattened and which are kept.
+
+A module that is not flattened, can be built separately without any
+loss in quality of results and combined as shown below. The module
+that is built separately be built with and without SYNTH_HIERARCHICAL=1.
+
+1. Synthesize aes_key_expand_128 module
+
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=blackbox clean_synth synth
+2. Synthesize top module, which could happen in parallel to 1 but with aes_key_expand_128 blacklisted:
+
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=top clean_synth synth
+3. Combine the synthesis results above:
+
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine clean_synth synth
+
+4. View final result:
+
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine
+       make DESIGN_CONFIG=designs/asap7/aes/config.mk FLOW_VARIANT=combine gui_final
+
+![alt text](final.png)

flow/designs/asap7/aes/BUILD.bazel

@@ -15,3 +15,17 @@ export PLACE_DENSITY            = 0.65
 export TNS_END_PERCENT          = 100
 export EQUIVALENCE_CHECK       ?=   1
 export REMOVE_CELLS_FOR_EQY     = TAPCELL*
+
+ifeq ($(FLOW_VARIANT),top)
+	export DESIGN_NAME = aes_cipher_top
+	export SYNTH_BLACKBOXES = aes_key_expand_128
+else ifeq ($(FLOW_VARIANT),blackbox)
+	export DESIGN_NAME = aes_key_expand_128
+else ifeq ($(FLOW_VARIANT),combine)
+	export EQUIVALENCE_CHECK = 0
+# List blackbox twice to demonstrates that duplicate modules are ignored.
+	export SYNTH_NETLIST_FILES = \
+	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/top/1_synth.v \
+	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v \
+	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v
+endif