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Merge pull request #2418 from Pinata-Consulting/rtlmp-flow-default-fix
Rtlmp flow default fix
2 parents 789bc39 + 86b3600 commit dddca4a

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flow/designs/asap7/aes-block/config.mk

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@@ -15,7 +15,6 @@ export PLACE_DENSITY = 0.65
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export BLOCKS ?= aes_rcon aes_sbox
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export SYNTH_HIERARCHICAL = 1
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export RTLMP_FLOW = 1
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export PLACE_PINS_ARGS = -annealing
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flow/designs/asap7/riscv32i/config.mk

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@@ -3,7 +3,6 @@ export DESIGN_NAME = riscv_top
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export PLATFORM = asap7
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export SYNTH_HIERARCHICAL = 1
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export RTLMP_FLOW = 1
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export RTLMP_MIN_INST = 1000
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export RTLMP_MAX_INST = 3500

flow/designs/asap7/swerv_wrapper/config.mk

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@@ -2,7 +2,6 @@ export DESIGN_NAME = swerv_wrapper
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export PLATFORM = asap7
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export SYNTH_HIERARCHICAL = 1
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export RTLMP_FLOW = 1
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
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export RTLMP_MIN_INST = 5000

flow/designs/gf12/ariane/config.mk

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@@ -3,7 +3,6 @@ export PLATFORM = gf12
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export SYNTH_HIERARCHICAL = 1
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export MAX_UNGROUP_SIZE ?= 10000
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export RTLMP_FLOW = 1
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#
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export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \

flow/designs/gf12/ariane133/config.mk

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@@ -4,7 +4,6 @@ export PLATFORM = gf12
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export SYNTH_HIERARCHICAL = 1
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export MAX_UNGROUP_SIZE ?= 10000
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export RTLMP_FLOW = 1
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#
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# RTL_MP Settings
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flow/designs/gf12/bp_dual/config.mk

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@@ -4,7 +4,6 @@ export PLATFORM = gf12
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export SYNTH_HIERARCHICAL = 1
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#
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export RTLMP_FLOW = 1
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
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export RTLMP_MIN_INST = 10000

flow/designs/gf12/bp_quad/config.mk

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@@ -2,7 +2,6 @@ export DESIGN_NICKNAME = bp_quad
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export DESIGN_NAME = bsg_chip
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export PLATFORM = gf12
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export RTLMP_FLOW = 1
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export SYNTH_HIERARCHICAL = 1
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export MAX_UNGROUP_SIZE ?= 1000
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flow/designs/gf12/bp_single/config_mpl2.mk

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@@ -6,7 +6,6 @@ export SKIP_GATE_CLONING = 1
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export TNS_END_PERCENT = 5
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export SYNTH_HIERARCHICAL = 1
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export RTLMP_FLOW = 1
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#
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000

flow/designs/gf12/ca53/config.mk

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@@ -1,7 +1,6 @@
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export DESIGN_NAME = ca53_cpu
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export PLATFORM = gf12
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export RTLMP_FLOW = 1
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export VERILOG_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
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export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v

flow/designs/gf12/swerv_wrapper/config.mk

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@@ -3,7 +3,6 @@ export PLATFORM = gf12
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#
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export MAX_UNGROUP_SIZE ?= 10000
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export SYNTH_HIERARCHICAL = 1
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export RTLMP_FLOW = 1
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# RTL_MP Settings
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export RTLMP_MAX_INST = 25000

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