flow: Tighten a number of designs with positive WS

povik · povik · commit de969a808107 · 2025-03-17T19:58:58.000+01:00
Signed-off-by: Martin Povišer &lt;povik@cutebit.org&gt;
diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk 
 set clk_port_name clk
-set clk_period 1100 
+set clk_period 900
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 6 
+set clk_period 6
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc
@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name  core_clock
 set clk_port_name clk_i
-set clk_period 10.75
+set clk_period 10.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc b/flow/designs/ihp-sg13g2/riscv32i/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 10.0 
+set clk_period 7.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk 
 set clk_port_name clk
-set clk_period 1.4 
+set clk_period 1.2
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc
@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk 
 set clk_port_name clk
-set clk_period 7.5 
+set clk_period 6.5
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc
@@ -2,7 +2,7 @@ current_design aes_cipher_top
 
 set clk_name  clk
 set clk_port_name clk
-set clk_period 4.0 
+set clk_period 3.6
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc
@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name  core_clock
 set clk_port_name clk_i
-set clk_period 11.8 
+set clk_period 11.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
diff --git a/flow/designs/sky130hs/riscv32i/constraint.sdc b/flow/designs/sky130hs/riscv32i/constraint.sdc
@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 7.6 
+set clk_period 6.2
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]
