Skip to content

Commit ec942a0

Browse files
authored
Merge pull request #1851 from The-OpenROAD-Project-staging/vanilla5-mpl2
Enable mpl2 for vanilla5
2 parents 12c7d2e + 456926b commit ec942a0

File tree

3 files changed

+416
-0
lines changed

3 files changed

+416
-0
lines changed

flow/designs/tsmc65lp/vanilla5/config.mk

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,10 @@ export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg10_w32_all.gds2 \
1515
$(PLATFORM_DIR)/gds/tsmc65lp_2rf_lg5_w32_all.gds2 \
1616
$(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg10_w32_byte.gds2
1717

18+
export SYNTH_HIERARCHICAL = 1
19+
20+
export RTLMP_FLOW = True
21+
1822
# These values must be multiples of placement site
1923
export DIE_AREA = 0 0 1100 400.8
2024
export CORE_AREA = 10 12 1090 391.2
Lines changed: 354 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,354 @@
1+
{
2+
"constraints__clocks__count": 1,
3+
"constraints__clocks__details": [
4+
"core_clk: 8.0000"
5+
],
6+
"cts__clock__skew__hold": 0.155967,
7+
"cts__clock__skew__hold__post_repair": 0.156257,
8+
"cts__clock__skew__hold__pre_repair": 0.156257,
9+
"cts__clock__skew__setup": 0.27008,
10+
"cts__clock__skew__setup__post_repair": 0.27037,
11+
"cts__clock__skew__setup__pre_repair": 0.27037,
12+
"cts__cpu__total": 18.03,
13+
"cts__design__core__area": 409536,
14+
"cts__design__core__area__post_repair": 409536,
15+
"cts__design__core__area__pre_repair": 409536,
16+
"cts__design__die__area": 440880,
17+
"cts__design__die__area__post_repair": 440880,
18+
"cts__design__die__area__pre_repair": 440880,
19+
"cts__design__instance__area": 192986,
20+
"cts__design__instance__area__macros": 64603.9,
21+
"cts__design__instance__area__macros__post_repair": 64603.9,
22+
"cts__design__instance__area__macros__pre_repair": 64603.9,
23+
"cts__design__instance__area__post_repair": 192986,
24+
"cts__design__instance__area__pre_repair": 192986,
25+
"cts__design__instance__area__stdcell": 128382,
26+
"cts__design__instance__area__stdcell__post_repair": 128382,
27+
"cts__design__instance__area__stdcell__pre_repair": 128382,
28+
"cts__design__instance__count": 18446,
29+
"cts__design__instance__count__hold_buffer": 0,
30+
"cts__design__instance__count__macros": 4,
31+
"cts__design__instance__count__macros__post_repair": 4,
32+
"cts__design__instance__count__macros__pre_repair": 4,
33+
"cts__design__instance__count__post_repair": 18446,
34+
"cts__design__instance__count__pre_repair": 18446,
35+
"cts__design__instance__count__setup_buffer": 0,
36+
"cts__design__instance__count__stdcell": 18442,
37+
"cts__design__instance__count__stdcell__post_repair": 18442,
38+
"cts__design__instance__count__stdcell__pre_repair": 18442,
39+
"cts__design__instance__displacement__max": 0,
40+
"cts__design__instance__displacement__mean": 0,
41+
"cts__design__instance__displacement__total": 0,
42+
"cts__design__instance__utilization": 0.47123,
43+
"cts__design__instance__utilization__post_repair": 0.47123,
44+
"cts__design__instance__utilization__pre_repair": 0.47123,
45+
"cts__design__instance__utilization__stdcell": 0.372194,
46+
"cts__design__instance__utilization__stdcell__post_repair": 0.372194,
47+
"cts__design__instance__utilization__stdcell__pre_repair": 0.372194,
48+
"cts__design__io": 723,
49+
"cts__design__io__post_repair": 723,
50+
"cts__design__io__pre_repair": 723,
51+
"cts__design__violations": 0,
52+
"cts__mem__peak": 449176.0,
53+
"cts__power__internal__total": 9.79332e-05,
54+
"cts__power__internal__total__post_repair": 9.79335e-05,
55+
"cts__power__internal__total__pre_repair": 9.79335e-05,
56+
"cts__power__leakage__total": 0.000140348,
57+
"cts__power__leakage__total__post_repair": 0.000140348,
58+
"cts__power__leakage__total__pre_repair": 0.000140348,
59+
"cts__power__switching__total": 7.8039e-05,
60+
"cts__power__switching__total__post_repair": 7.80356e-05,
61+
"cts__power__switching__total__pre_repair": 7.80356e-05,
62+
"cts__power__total": 0.00031632,
63+
"cts__power__total__post_repair": 0.000316317,
64+
"cts__power__total__pre_repair": 0.000316317,
65+
"cts__route__wirelength__estimated": 562635,
66+
"cts__runtime__total": "0:18.46",
67+
"cts__timing__drv__hold_violation_count": 3,
68+
"cts__timing__drv__hold_violation_count__post_repair": 3,
69+
"cts__timing__drv__hold_violation_count__pre_repair": 3,
70+
"cts__timing__drv__max_cap": 0,
71+
"cts__timing__drv__max_cap__post_repair": 0,
72+
"cts__timing__drv__max_cap__pre_repair": 0,
73+
"cts__timing__drv__max_cap_limit": 0.945326,
74+
"cts__timing__drv__max_cap_limit__post_repair": 0.947111,
75+
"cts__timing__drv__max_cap_limit__pre_repair": 0.947111,
76+
"cts__timing__drv__max_fanout": 83,
77+
"cts__timing__drv__max_fanout__post_repair": 83,
78+
"cts__timing__drv__max_fanout__pre_repair": 83,
79+
"cts__timing__drv__max_fanout_limit": 12,
80+
"cts__timing__drv__max_fanout_limit__post_repair": 12,
81+
"cts__timing__drv__max_fanout_limit__pre_repair": 12,
82+
"cts__timing__drv__max_slew": 3160,
83+
"cts__timing__drv__max_slew__post_repair": 3081,
84+
"cts__timing__drv__max_slew__pre_repair": 3081,
85+
"cts__timing__drv__max_slew_limit": -19.8425,
86+
"cts__timing__drv__max_slew_limit__post_repair": -19.841,
87+
"cts__timing__drv__max_slew_limit__pre_repair": -19.841,
88+
"cts__timing__drv__setup_violation_count": 0,
89+
"cts__timing__drv__setup_violation_count__post_repair": 0,
90+
"cts__timing__drv__setup_violation_count__pre_repair": 0,
91+
"cts__timing__setup__tns": 0,
92+
"cts__timing__setup__tns__post_repair": 0,
93+
"cts__timing__setup__tns__pre_repair": 0,
94+
"cts__timing__setup__ws": 3.2267,
95+
"cts__timing__setup__ws__post_repair": 3.23799,
96+
"cts__timing__setup__ws__pre_repair": 3.23799,
97+
"design__io__hpwl": 156676237,
98+
"detailedplace__cpu__total": 14.28,
99+
"detailedplace__design__core__area": 409536,
100+
"detailedplace__design__die__area": 440880,
101+
"detailedplace__design__instance__area": 191386,
102+
"detailedplace__design__instance__area__macros": 64603.9,
103+
"detailedplace__design__instance__area__stdcell": 126782,
104+
"detailedplace__design__instance__count": 18348,
105+
"detailedplace__design__instance__count__macros": 4,
106+
"detailedplace__design__instance__count__stdcell": 18344,
107+
"detailedplace__design__instance__displacement__max": 48.5,
108+
"detailedplace__design__instance__displacement__mean": 3.0425,
109+
"detailedplace__design__instance__displacement__total": 55826.9,
110+
"detailedplace__design__instance__utilization": 0.467325,
111+
"detailedplace__design__instance__utilization__stdcell": 0.367558,
112+
"detailedplace__design__io": 723,
113+
"detailedplace__design__violations": 0,
114+
"detailedplace__mem__peak": 419900.0,
115+
"detailedplace__power__internal__total": 0.00411216,
116+
"detailedplace__power__leakage__total": 0.000125683,
117+
"detailedplace__power__switching__total": 0.0136291,
118+
"detailedplace__power__total": 0.0178669,
119+
"detailedplace__route__wirelength__estimated": 573262,
120+
"detailedplace__runtime__total": "0:14.59",
121+
"detailedplace__timing__drv__hold_violation_count": 6,
122+
"detailedplace__timing__drv__max_cap": 0,
123+
"detailedplace__timing__drv__max_cap_limit": 0.947111,
124+
"detailedplace__timing__drv__max_fanout": 0,
125+
"detailedplace__timing__drv__max_fanout_limit": 12,
126+
"detailedplace__timing__drv__max_slew": 2987,
127+
"detailedplace__timing__drv__max_slew_limit": -19.841,
128+
"detailedplace__timing__drv__setup_violation_count": 0,
129+
"detailedplace__timing__setup__tns": 0,
130+
"detailedplace__timing__setup__ws": 1.84568,
131+
"detailedroute__cpu__total": 702.82,
132+
"detailedroute__mem__peak": 2388560.0,
133+
"detailedroute__route__drc_errors": 0,
134+
"detailedroute__route__drc_errors__iter:1": 3997,
135+
"detailedroute__route__drc_errors__iter:2": 127,
136+
"detailedroute__route__drc_errors__iter:3": 35,
137+
"detailedroute__route__drc_errors__iter:4": 0,
138+
"detailedroute__route__net": 17557,
139+
"detailedroute__route__net__special": 2,
140+
"detailedroute__route__vias": 111924,
141+
"detailedroute__route__vias__multicut": 0,
142+
"detailedroute__route__vias__singlecut": 111924,
143+
"detailedroute__route__wirelength": 631800,
144+
"detailedroute__route__wirelength__iter:1": 633853,
145+
"detailedroute__route__wirelength__iter:2": 631885,
146+
"detailedroute__route__wirelength__iter:3": 631809,
147+
"detailedroute__route__wirelength__iter:4": 631800,
148+
"detailedroute__runtime__total": "0:39.31",
149+
"fillcell__cpu__total": 3.21,
150+
"fillcell__mem__peak": 389072.0,
151+
"fillcell__runtime__total": "0:03.47",
152+
"finish__clock__skew__hold": 0.114112,
153+
"finish__clock__skew__setup": 0.191697,
154+
"finish__cpu__total": 16.76,
155+
"finish__design__core__area": 409536,
156+
"finish__design__die__area": 440880,
157+
"finish__design__instance__area": 196370,
158+
"finish__design__instance__area__macros": 64603.9,
159+
"finish__design__instance__area__stdcell": 131766,
160+
"finish__design__instance__count": 19156,
161+
"finish__design__instance__count__macros": 4,
162+
"finish__design__instance__count__stdcell": 19152,
163+
"finish__design__instance__utilization": 0.479494,
164+
"finish__design__instance__utilization__stdcell": 0.382006,
165+
"finish__design__io": 723,
166+
"finish__mem__peak": 697536.0,
167+
"finish__power__internal__total": 9.66525e-05,
168+
"finish__power__leakage__total": 0.000144127,
169+
"finish__power__switching__total": 4.95536e-05,
170+
"finish__power__total": 0.000290333,
171+
"finish__runtime__total": "0:18.00",
172+
"finish__timing__drv__hold_violation_count": 4,
173+
"finish__timing__drv__max_cap": 0,
174+
"finish__timing__drv__max_cap_limit": 0.964667,
175+
"finish__timing__drv__max_fanout": 0,
176+
"finish__timing__drv__max_fanout_limit": 12,
177+
"finish__timing__drv__max_slew": 3454,
178+
"finish__timing__drv__max_slew_limit": -21.0255,
179+
"finish__timing__drv__setup_violation_count": 0,
180+
"finish__timing__setup__tns": 0,
181+
"finish__timing__setup__ws": 3.38196,
182+
"finish__timing__wns_percent_delay": 79.185203,
183+
"finish_merge__cpu__total": 6.43,
184+
"finish_merge__mem__peak": 661132.0,
185+
"finish_merge__runtime__total": "0:06.93",
186+
"floorplan__cpu__total": 5.85,
187+
"floorplan__design__core__area": 409536,
188+
"floorplan__design__die__area": 440880,
189+
"floorplan__design__instance__area": 137079,
190+
"floorplan__design__instance__area__macros": 64603.9,
191+
"floorplan__design__instance__area__stdcell": 72474.7,
192+
"floorplan__design__instance__count": 11145,
193+
"floorplan__design__instance__count__macros": 4,
194+
"floorplan__design__instance__count__stdcell": 11141,
195+
"floorplan__design__instance__utilization": 0.334717,
196+
"floorplan__design__instance__utilization__stdcell": 0.210113,
197+
"floorplan__design__io": 723,
198+
"floorplan__mem__peak": 364784.0,
199+
"floorplan__power__internal__total": 0.0032858,
200+
"floorplan__power__leakage__total": 6.49171e-05,
201+
"floorplan__power__switching__total": 0.0127637,
202+
"floorplan__power__total": 0.0161144,
203+
"floorplan__runtime__total": "0:06.10",
204+
"floorplan__timing__setup__tns": -1019.09,
205+
"floorplan__timing__setup__ws": -8.40701,
206+
"floorplan_io__cpu__total": 2.99,
207+
"floorplan_io__mem__peak": 330564.0,
208+
"floorplan_io__runtime__total": "0:03.18",
209+
"floorplan_macro__cpu__total": 598.52,
210+
"floorplan_macro__mem__peak": 443868.0,
211+
"floorplan_macro__runtime__total": "6:47.98",
212+
"floorplan_pdn__cpu__total": 3.52,
213+
"floorplan_pdn__mem__peak": 360868.0,
214+
"floorplan_pdn__runtime__total": "0:03.72",
215+
"floorplan_tap__cpu__total": 3.04,
216+
"floorplan_tap__mem__peak": 323240.0,
217+
"floorplan_tap__runtime__total": "0:03.22",
218+
"globalplace__cpu__total": 94.04,
219+
"globalplace__design__core__area": 409536,
220+
"globalplace__design__die__area": 440880,
221+
"globalplace__design__instance__area": 139085,
222+
"globalplace__design__instance__area__macros": 64603.9,
223+
"globalplace__design__instance__area__stdcell": 74481.1,
224+
"globalplace__design__instance__count": 13235,
225+
"globalplace__design__instance__count__macros": 4,
226+
"globalplace__design__instance__count__stdcell": 13231,
227+
"globalplace__design__instance__utilization": 0.339616,
228+
"globalplace__design__instance__utilization__stdcell": 0.21593,
229+
"globalplace__design__io": 723,
230+
"globalplace__mem__peak": 585184.0,
231+
"globalplace__power__internal__total": 0.00335339,
232+
"globalplace__power__leakage__total": 6.49171e-05,
233+
"globalplace__power__switching__total": 0.0131306,
234+
"globalplace__power__total": 0.0165489,
235+
"globalplace__runtime__total": "1:04.45",
236+
"globalplace__timing__setup__tns": -2118.93,
237+
"globalplace__timing__setup__ws": -8.73259,
238+
"globalplace_io__cpu__total": 3.0,
239+
"globalplace_io__mem__peak": 336168.0,
240+
"globalplace_io__runtime__total": "0:03.22",
241+
"globalplace_skip_io__cpu__total": 5.84,
242+
"globalplace_skip_io__mem__peak": 347672.0,
243+
"globalplace_skip_io__runtime__total": "0:06.11",
244+
"globalroute__antenna__violating__nets": 0,
245+
"globalroute__antenna__violating__pins": 0,
246+
"globalroute__clock__skew__hold": 0.157952,
247+
"globalroute__clock__skew__setup": 0.272065,
248+
"globalroute__cpu__total": 34.71,
249+
"globalroute__design__core__area": 409536,
250+
"globalroute__design__die__area": 440880,
251+
"globalroute__design__instance__area": 196370,
252+
"globalroute__design__instance__area__macros": 64603.9,
253+
"globalroute__design__instance__area__stdcell": 131766,
254+
"globalroute__design__instance__count": 19156,
255+
"globalroute__design__instance__count__hold_buffer": 0,
256+
"globalroute__design__instance__count__macros": 4,
257+
"globalroute__design__instance__count__setup_buffer": 0,
258+
"globalroute__design__instance__count__stdcell": 19152,
259+
"globalroute__design__instance__displacement__max": 0,
260+
"globalroute__design__instance__displacement__mean": 0,
261+
"globalroute__design__instance__displacement__total": 0,
262+
"globalroute__design__instance__utilization": 0.479494,
263+
"globalroute__design__instance__utilization__stdcell": 0.382006,
264+
"globalroute__design__io": 723,
265+
"globalroute__design__violations": 0,
266+
"globalroute__mem__peak": 755772.0,
267+
"globalroute__power__internal__total": 9.76494e-05,
268+
"globalroute__power__leakage__total": 0.000144103,
269+
"globalroute__power__switching__total": 7.96264e-05,
270+
"globalroute__power__total": 0.000321379,
271+
"globalroute__route__wirelength__estimated": 578734,
272+
"globalroute__runtime__total": "0:39.76",
273+
"globalroute__timing__clock__slack": 3.166,
274+
"globalroute__timing__drv__hold_violation_count": 4,
275+
"globalroute__timing__drv__max_cap": 0,
276+
"globalroute__timing__drv__max_cap_limit": 0.957725,
277+
"globalroute__timing__drv__max_fanout": 0,
278+
"globalroute__timing__drv__max_fanout_limit": 12,
279+
"globalroute__timing__drv__max_slew": 4770,
280+
"globalroute__timing__drv__max_slew_limit": -21.603,
281+
"globalroute__timing__drv__setup_violation_count": 0,
282+
"globalroute__timing__setup__tns": 0,
283+
"globalroute__timing__setup__ws": 3.16597,
284+
"placeopt__cpu__total": 15.78,
285+
"placeopt__design__core__area": 409536,
286+
"placeopt__design__core__area__pre_opt": 409536,
287+
"placeopt__design__die__area": 440880,
288+
"placeopt__design__die__area__pre_opt": 440880,
289+
"placeopt__design__instance__area": 191386,
290+
"placeopt__design__instance__area__macros": 64603.9,
291+
"placeopt__design__instance__area__macros__pre_opt": 64603.9,
292+
"placeopt__design__instance__area__pre_opt": 139085,
293+
"placeopt__design__instance__area__stdcell": 126782,
294+
"placeopt__design__instance__area__stdcell__pre_opt": 74481.1,
295+
"placeopt__design__instance__count": 18348,
296+
"placeopt__design__instance__count__macros": 4,
297+
"placeopt__design__instance__count__macros__pre_opt": 4,
298+
"placeopt__design__instance__count__pre_opt": 13235,
299+
"placeopt__design__instance__count__stdcell": 18344,
300+
"placeopt__design__instance__count__stdcell__pre_opt": 13231,
301+
"placeopt__design__instance__utilization": 0.467325,
302+
"placeopt__design__instance__utilization__pre_opt": 0.339616,
303+
"placeopt__design__instance__utilization__stdcell": 0.367558,
304+
"placeopt__design__instance__utilization__stdcell__pre_opt": 0.21593,
305+
"placeopt__design__io": 723,
306+
"placeopt__design__io__pre_opt": 723,
307+
"placeopt__mem__peak": 414840.0,
308+
"placeopt__power__internal__total": 0.00372039,
309+
"placeopt__power__internal__total__pre_opt": 0.00335339,
310+
"placeopt__power__leakage__total": 0.000124698,
311+
"placeopt__power__leakage__total__pre_opt": 6.49171e-05,
312+
"placeopt__power__switching__total": 0.000769801,
313+
"placeopt__power__switching__total__pre_opt": 0.0131306,
314+
"placeopt__power__total": 0.00461489,
315+
"placeopt__power__total__pre_opt": 0.0165489,
316+
"placeopt__runtime__total": "0:16.18",
317+
"placeopt__timing__drv__floating__nets": 0,
318+
"placeopt__timing__drv__floating__pins": 3,
319+
"placeopt__timing__drv__hold_violation_count": 6,
320+
"placeopt__timing__drv__max_cap": 0,
321+
"placeopt__timing__drv__max_cap_limit": 0.9643,
322+
"placeopt__timing__drv__max_fanout": 0,
323+
"placeopt__timing__drv__max_fanout_limit": 12,
324+
"placeopt__timing__drv__max_slew": 2869,
325+
"placeopt__timing__drv__max_slew_limit": -19.2127,
326+
"placeopt__timing__drv__setup_violation_count": 0,
327+
"placeopt__timing__setup__tns": -0.00219913,
328+
"placeopt__timing__setup__tns__pre_opt": -2118.93,
329+
"placeopt__timing__setup__ws": 1.84617,
330+
"placeopt__timing__setup__ws__pre_opt": -8.73259,
331+
"run__flow__design": "vanilla5",
332+
"run__flow__generate_date": "2024-03-17 22:44",
333+
"run__flow__metrics_version": "Metrics_2.1.2",
334+
"run__flow__openroad_commit": "N/A",
335+
"run__flow__openroad_version": "v2.0-12608-g50753a4c5",
336+
"run__flow__platform": "tsmc65lp",
337+
"run__flow__platform__capacitance_units": "1pF",
338+
"run__flow__platform__current_units": "1mA",
339+
"run__flow__platform__distance_units": "1um",
340+
"run__flow__platform__power_units": "1uW",
341+
"run__flow__platform__resistance_units": "1kohm",
342+
"run__flow__platform__time_units": "1ns",
343+
"run__flow__platform__voltage_units": "1v",
344+
"run__flow__platform_commit": "730fc586e5c9b66fa3a4f855f18f25797b654914",
345+
"run__flow__scripts_commit": "12c7d2e07c59991900627e30a4c3ed0a657448f8",
346+
"run__flow__uuid": "00dcc2f8-5fd4-4b5a-b5cd-84916072f40f",
347+
"run__flow__variant": "base",
348+
"synth__cpu__total": 54.15,
349+
"synth__design__instance__area__stdcell": 142008.6506,
350+
"synth__design__instance__count__stdcell": 12354.0,
351+
"synth__mem__peak": 275552.0,
352+
"synth__runtime__total": "0:54.81",
353+
"total_time": "0:11:49.490000"
354+
}

0 commit comments

Comments
 (0)