add max fanout constraint to asap7/cva6 to validate new crit VT swap

precisionmoon · precisionmoon · commit fe62c12d8b09 · 2025-09-20T05:18:57.000Z
Signed-off-by: Cho Moon &lt;cmoon@precisioninno.com&gt;
diff --git a/flow/designs/asap7/cva6/config.mk b/flow/designs/asap7/cva6/config.mk
@@ -95,7 +95,7 @@ export PLACE_DENSITY          = 0.69
 
 # a smoketest for this option, there are a
 # few last gasp iterations
-export SKIP_LAST_GASP ?= 1
+#export SKIP_LAST_GASP ?= 1
 
 # For use with SYNTH_HIERARCHICAL
 export SYNTH_MINIMUM_KEEP_SIZE ?= 40000
diff --git a/flow/designs/asap7/cva6/constraint.sdc b/flow/designs/asap7/cva6/constraint.sdc
@@ -34,3 +34,4 @@ create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
 
 
 set_false_path -to [get_ports {rvfi_probes_o}]
+set_max_fanout 10 [current_design]
diff --git a/tools/OpenROAD b/tools/OpenROAD
@@ -1 +1 @@
-Subproject commit 96512a37e909391e63c0e2431b3850779216a465
+Subproject commit a5073ecab3cefeb441228b352255458b2ead2db1

Original file line number	Diff line number	Diff line change
`@@ -34,3 +34,4 @@ create_clock [get_ports $clk_port] -name $clk_name -period $clk_period`
`34`	`34`
`35`	`35`
`36`	`36`	`set_false_path -to [get_ports {rvfi_probes_o}]`
	`37`	`+set_max_fanout 10 [current_design]`