synth: add SYNTH_MOCK_LARGE_MEMORIES

flow/designs/sky130hd/microwatt/config.mk

@@ -36,7 +36,4 @@ export SETUP_SLACK_MARGIN = 0.2
 # GRT non-default config
 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
 
-# This is high, some SRAMs should probably be converted
-# to real SRAMs and not instantiated as flops
-export SYNTH_MEMORY_MAX_BITS = 42000
-
+export SYNTH_MOCK_LARGE_MEMORIES = 1

flow/scripts/synth.tcl

@@ -55,6 +55,25 @@ if { !$::env(SYNTH_HIERARCHICAL) } {
   synth -flatten -run coarse:fine {*}$synth_full_args
 }
 
+
+if { $::env(SYNTH_MOCK_LARGE_MEMORIES) } {
+  memory_collect
+  foreach path [tee -q -s result.string select -list t:\$mem_v2] {
+    set index [string first "/" $path]
+    set module [string range $path 0 [expr {$index - 1}]]
+    set instance [string range $path [expr {$index + 1}] end]
+
+    set width [rtlil::get_param -uint $module $instance WIDTH]
+    set size [rtlil::get_param -uint $module $instance SIZE]
+    set nbits [expr $width * $size]
+    puts "Memory $path has dimensions $size x $width = $nbits"
+    if {$nbits > $::env(SYNTH_MEMORY_MAX_BITS)} {
+      rtlil::set_param -uint $module $instance SIZE 1
+      puts "Shrunk memory $path from $size rows to 1"
+    }
+  }
+}
+
 json -o $::env(RESULTS_DIR)/mem.json
 # Run report and check here so as to fail early if this synthesis run is doomed
 exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \

flow/scripts/variables.yaml

@@ -177,6 +177,22 @@ SYNTH_MEMORY_MAX_BITS:
   default: 4096
   stages:
     - synth
+SYNTH_MOCK_LARGE_MEMORIES:
+  description: >
+    Reduce memories larger than SYNTH_MEMORY_MAX_BITS to 1 row.
+
+    This is useful to separate the concern of instantiating and placing
+    memories from investigating other issues with a design.
+
+    Memories with a single 1 row will of course have unrealistically good
+    timing and area characteristics, but timing will still correctly terminate
+    in a register.
+
+    Also, large port memories, typically register files, will still have the
+    retain a lot of the port logic that can be useful to investigate issues.
+  default: 0
+  stages:
+    - synth
 SYNTH_HDL_FRONTEND:
   description: >
     Select an alternative language frontend to ingest the design. Available option