Skip to content

Commit 2bec092

Browse files
malibertymaliberty
authored
Merge pull request #9012 from Pinata-Consulting/test-orfs-gcd-eqy-fixes
Test orfs gcd eqy fixes
2 parents 61879be + 1d63e3c commit 2bec092

File tree

14 files changed

+163
-108
lines changed

14 files changed

+163
-108
lines changed

‎test/orfs/BUILD‎

Whitespace-only changes.

‎test/orfs/asap7/BUILD‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
filegroup(
2+
name = "asap7_files",
3+
srcs = [
4+
"asap7sc7p5t_AO_RVT_TT_201020.v",
5+
"asap7sc7p5t_INVBUF_RVT_TT_201020.v",
6+
"asap7sc7p5t_OA_RVT_TT_201020.v",
7+
"asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
8+
"@docker_orfs//:OpenROAD-flow-scripts/flow/platforms/asap7/verilog/stdcell/dff.v",
9+
],
10+
visibility = ["//visibility:public"],
11+
)

test/orfs/mock-array/asap7/README.md renamed to test/orfs/asap7/README.md

File renamed without changes.

‎test/orfs/asap7/asap7.bzl‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
"""
2+
asap7 shared info
3+
"""
4+
5+
# Empty cells we don't need or want, eqy doesn't grok them
6+
ASAP7_REMOVE_CELLS = [
7+
"TAPCELL_ASAP7_75t_R",
8+
"FILLERxp5_ASAP7_75",
9+
"FILLER_ASAP7_75t_R",
10+
"DECAPx1_ASAP7_75t_R",
11+
"DECAPx2_ASAP7_75t_R",
12+
"DECAPx4_ASAP7_75t_R",
13+
"DECAPx6_ASAP7_75t_R",
14+
"DECAPx10_ASAP7_75t_R",
15+
"FILLERxp5_ASAP7_75t_R",
16+
]

test/orfs/mock-array/asap7/asap7sc7p5t_AO_RVT_TT_201020.v renamed to test/orfs/asap7/asap7sc7p5t_AO_RVT_TT_201020.v

File renamed without changes.

test/orfs/mock-array/asap7/asap7sc7p5t_INVBUF_RVT_TT_201020.v renamed to test/orfs/asap7/asap7sc7p5t_INVBUF_RVT_TT_201020.v

File renamed without changes.

test/orfs/mock-array/asap7/asap7sc7p5t_OA_RVT_TT_201020.v renamed to test/orfs/asap7/asap7sc7p5t_OA_RVT_TT_201020.v

File renamed without changes.

test/orfs/mock-array/asap7/asap7sc7p5t_SIMPLE_RVT_TT_201020.v renamed to test/orfs/asap7/asap7sc7p5t_SIMPLE_RVT_TT_201020.v

File renamed without changes.

‎test/orfs/eqy-flow.bzl‎

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
"""
2+
This module defines the ORFS equivalence for orfs_flow() using EQY and OpenROAD.
3+
"""
4+
5+
load("@bazel-orfs//:eqy.bzl", "eqy_test")
6+
load("@bazel-orfs//:openroad.bzl", "orfs_run")
7+
load("//test/orfs/asap7:asap7.bzl", "ASAP7_REMOVE_CELLS")
8+
9+
STAGES = [
10+
"source",
11+
# _source tests original source to source transition,
12+
# which checks that the eqy setup works.
13+
"source",
14+
# _synth tests synthesis output, and so on
15+
# for the next stages.
16+
"synth",
17+
"floorplan",
18+
"place",
19+
"cts",
20+
"grt",
21+
"route",
22+
"final",
23+
]
24+
25+
def eqy_flow_test(name, flow, verilog_files, module_top, other_verilog_files = [], **kwargs):
26+
"""Defines ORFS equivalence checking flow tests for a given design.
27+
28+
Args:
29+
name: name stem for rules setup by this macro
30+
flow: orfs_flow(name, ...)
31+
verilog_files: List of verilog files needed for synthesis.
32+
module_top: Top-level module name for the design.
33+
other_verilog_files: other gate netlists needed, typically macros, default is [].
34+
**kwargs: Additional keyword arguments passed to eqy_test and test_suite.
35+
"""
36+
for stage in STAGES[2:]:
37+
orfs_run(
38+
name = "{name}_{stage}_verilog".format(stage = stage, name = name),
39+
src = ":{flow}_{stage}".format(stage = stage, flow = flow),
40+
outs = [
41+
"{name}_{stage}.v".format(stage = stage, name = name),
42+
],
43+
arguments = {
44+
"ASAP7_REMOVE_CELLS": " ".join(ASAP7_REMOVE_CELLS),
45+
"OUTPUT": "$(location :{name}_{stage}.v)".format(stage = stage, name = name),
46+
},
47+
script = "//test/orfs/mock-array:write_verilog.tcl",
48+
tags = ["manual"],
49+
)
50+
51+
native.filegroup(
52+
name = "{name}_{stage}_files".format(stage = stage, name = name),
53+
srcs = [
54+
":{name}_{stage}_verilog".format(stage = stage, name = name),
55+
],
56+
tags = ["manual"],
57+
)
58+
59+
native.filegroup(
60+
name = "{name}_source_files".format(name = name),
61+
srcs = verilog_files + other_verilog_files,
62+
tags = ["manual"],
63+
)
64+
65+
for i in range(len(STAGES) - 1):
66+
eqy_test(
67+
name = "{name}_{stage}_test".format(stage = STAGES[i + 1], name = name),
68+
depth = 1,
69+
gate_verilog_files = [
70+
":{name}_{stage}_files".format(stage = STAGES[i + 1], name = name),
71+
"//test/orfs/asap7:asap7_files",
72+
] + other_verilog_files,
73+
gold_verilog_files = [
74+
":{name}_{stage}_files".format(stage = STAGES[i], name = name),
75+
"//test/orfs/asap7:asap7_files",
76+
] + other_verilog_files,
77+
module_top = module_top,
78+
**kwargs
79+
)
80+
81+
native.test_suite(
82+
name = "{name}_tests".format(name = name),
83+
tests = [
84+
"{name}_{stage}_test".format(stage = STAGES[i + 1], name = name)
85+
for i in range(len(STAGES) - 1)
86+
],
87+
**kwargs
88+
)

‎test/orfs/gcd/BUILD‎

Lines changed: 7 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
1-
load("@bazel-orfs//:eqy.bzl", "eqy_test")
2-
load("@bazel-orfs//:openroad.bzl", "orfs_flow", "orfs_run")
3-
load("//test/orfs/mock-array:mock-array.bzl", "ASAP7_REMOVE_CELLS")
1+
load("@bazel-orfs//:openroad.bzl", "orfs_flow")
2+
load("//test/orfs:eqy-flow.bzl", "eqy_flow_test")
43

54
package(features = ["layering_check"])
65

@@ -25,59 +24,10 @@ orfs_flow(
2524
verilog_files = ["gcd.v"],
2625
)
2726

28-
STAGES = [
29-
"source",
30-
# _source tests original source to source transition,
31-
# which checks that the eqy setup works.
32-
"source",
33-
# _synth tests synthesis output, and so on
34-
# for the next stages.
35-
"synth",
36-
"floorplan",
37-
"place",
38-
"cts",
39-
"grt",
40-
"route",
41-
"final",
42-
]
43-
44-
[orfs_run(
45-
name = "gcd_{stage}_verilog".format(stage = stage),
46-
src = ":gcd_{stage}".format(stage = stage),
47-
outs = [
48-
"gcd_{stage}.v".format(stage = stage),
49-
],
50-
arguments = {
51-
"ASAP7_REMOVE_CELLS": " ".join(ASAP7_REMOVE_CELLS),
52-
"OUTPUT": "$(location :gcd_{stage}.v)".format(stage = stage),
53-
},
54-
script = "//test/orfs/mock-array:write_verilog.tcl",
55-
tags = ["manual"],
56-
) for stage in STAGES[2:]]
57-
58-
filegroup(
59-
name = "gcd_source_files",
60-
srcs = [
61-
"gcd.v",
62-
],
63-
)
64-
65-
[filegroup(
66-
name = "gcd_{stage}_files".format(stage = stage),
67-
srcs = [
68-
":gcd_{stage}_verilog".format(stage = stage),
69-
],
70-
) for stage in STAGES[2:]]
71-
72-
[eqy_test(
73-
name = "eqy_{stage}_test".format(stage = STAGES[i + 1]),
74-
depth = 1,
75-
gate_verilog_files = [
76-
":gcd_{stage}_files".format(stage = STAGES[i + 1]),
77-
] + ([] if STAGES[i + 1] == "source" else ["//test/orfs/mock-array:asap7_files"]),
78-
gold_verilog_files = [
79-
":gcd_{stage}_files".format(stage = STAGES[i]),
80-
] + ([] if STAGES[i] == "source" else ["//test/orfs/mock-array:asap7_files"]),
27+
eqy_flow_test(
28+
name = "gcd_eqy",
29+
flow = "gcd",
8130
module_top = "gcd",
8231
tags = ["manual"],
83-
) for i in range(len(STAGES) - 1)]
32+
verilog_files = ["gcd.v"],
33+
)

0 commit comments

Comments
 (0)