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Merge pull request #367 from The-OpenROAD-Project/merge_openroad
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.clang-format

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---
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Language: Cpp
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BasedOnStyle: Google
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AlignConsecutiveAssignments: true
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AlignConsecutiveDeclarations: true
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AllowAllParametersOfDeclarationOnNextLine: false
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AllowShortFunctionsOnASingleLine: InlineOnly
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AllowShortIfStatementsOnASingleLine: false
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AllowShortLoopsOnASingleLine: false
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BinPackArguments: false
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BinPackParameters: false
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BraceWrapping:
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AfterClass: true
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AfterControlStatement: false
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AfterEnum: true
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AfterFunction: true
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AfterNamespace: false
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AfterObjCDeclaration: false
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AfterStruct: true
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AfterUnion: true
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AfterExternBlock: false
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BeforeCatch: false
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BeforeElse: false
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IndentBraces: false
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SplitEmptyFunction: true
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SplitEmptyRecord: true
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SplitEmptyNamespace: true
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BreakBeforeBinaryOperators: All
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BreakBeforeBraces: Custom
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DerivePointerAlignment: false
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SpaceAfterCStyleCast: true

CMakeLists.txt

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@@ -35,7 +35,7 @@ if(CMAKE_VERSION VERSION_GREATER_EQUAL 3.13)
3535
cmake_policy(SET CMP0077 NEW)
3636
endif()
3737

38-
project(OpenROAD VERSION 1.1.0
38+
project(OpenROAD VERSION 0.9.0
3939
LANGUAGES CXX
4040
)
4141

Dockerfile

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ LABEL maintainer="Abdelrahman Hosny <[email protected]>"
33

44
# Install dev and runtime dependencies
55
RUN yum group install -y "Development Tools" \
6-
&& yum install -y https://centos7.iuscommunity.org/ius-release.rpm \
6+
&& yum install -y https://repo.ius.io/ius-release-el7.rpm \
77
&& yum install -y centos-release-scl \
88
&& yum install -y wget devtoolset-8 \
99
devtoolset-8-libatomic-devel tcl-devel tcl tk libstdc++ tk-devel pcre-devel \
@@ -28,8 +28,8 @@ RUN wget https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm
2828
yum install -y epel-release-latest-7.noarch.rpm && rm -rf epel-release-latest-7.noarch.rpm \
2929
&& yum clean -y all
3030

31-
# Install git from epel
32-
RUN yum -y remove git && yum install -y git2u
31+
# Install any git version > 2.6.5
32+
RUN yum remove -y git* && yum install -y git224
3333

3434
# Install SWIG
3535
RUN yum remove -y swig \

README.md

Lines changed: 103 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -226,29 +226,41 @@ set_wire_rc [-layer layer_name]
226226
[-capacitance cap]
227227
[-corner corner_name]
228228
```
229+
229230
The `set_wire_rc` command sets the resistance and capacitance used to
230231
estimate delay of routing wires. Use `-layer` or `-resistance` and
231232
`-capacitance`. If `-layer` is used, the LEF technology resistance
232-
and area/edge capacitance values for the layer are used. The units
233-
for `-resistance` and `-capacitance` are from the first liberty file
234-
read, resistance_unit/distance_unit and liberty
235-
capacitance_unit/distance_unit. RC parasitics are added based on
236-
placed component pin locations. If there are no component locations no
237-
parasitics are added. The resistance and capacitance are per distance
238-
unit of a routing wire. Use the `set_units` command to check units or
239-
`set_cmd_units` to change units. They should represent "average"
240-
routing layer resistance and capacitance. If the set_wire_rc command
241-
is not called before resizing, the default_wireload model specified in
242-
the first liberty file or with the SDC set_wire_load command is used
243-
to make parasitics.
233+
and area/edge capacitance values for the layer are used for a minimum
234+
width wire on the layer. The resistance and capacitance values per
235+
length of wire, not per square or per square micron. The units for
236+
`-resistance` and `-capacitance` are from the first liberty file read,
237+
resistance_unit/distance_unit (typically kohms/micron) and liberty
238+
capacitance_unit/distance_unit (typically pf/micron or ff/micron). If
239+
no distance units are not specied in the liberty file microns are
240+
used.
241+
242+
```
243+
estimate_parasitics -placement
244+
```
245+
246+
Estimate RC parasitics based on placed component pin locations. If
247+
there are no component locations no parasitics are added. The
248+
resistance and capacitance are per distance unit of a routing
249+
wire. Use the `set_units` command to check units or `set_cmd_units` to
250+
change units. They should represent "average" routing layer resistance
251+
and capacitance. If the set_wire_rc command is not called before
252+
resizing, the default_wireload model specified in the first liberty
253+
file or with the SDC set_wire_load command is used to make parasitics.
244254

245255
```
246256
set_dont_use lib_cells
247257
```
248258

249-
The `set_dont_use` command removes library cells from consideration by the
250-
resizer. `lib_cells` is a list of cells returned by `get_lib_cells` or
251-
a list of cell names (wildcards allowed).
259+
The `set_dont_use` command removes library cells from consideration by
260+
the resizer. `lib_cells` is a list of cells returned by
261+
`get_lib_cells` or a list of cell names (wildcards allowed). For
262+
example, `DLY*` says do not use cells with names that begin with `DLY`
263+
in all libraries.
252264

253265
```
254266
buffer_ports [-inputs]
@@ -260,9 +272,24 @@ its loads. The `buffer_ports -outputs` adds a buffer between the port
260272
driver and the output port. If The default behavior is
261273
`-inputs` and `-outputs` if neither is specified.
262274

275+
```
276+
repair_design [-max_wire_length max_length]
277+
-buffer_cell buffer_cell
278+
```
279+
280+
The `repair_design` inserts buffers on nets to repair max slew, max
281+
capacitance, max fanout violations, and on long wires to reduce RC
282+
delay in the wire. Use `-max_wire_length` to specify the maximum lenth
283+
of wires. The resistance/capacitance values in `set_wire_rc` are used
284+
to find the wire delays.
285+
286+
Use the `set_max_fanout` SDC command to set the maximum fanout for the design.
287+
```
288+
set_max_fanout <fanout> [current_design]
289+
```
290+
263291
```
264292
resize [-libraries resize_libraries]
265-
[-dont_use cells]
266293
[-max_utilization util]
267294
```
268295
The `resize` command resizes gates to normalize slews.
@@ -272,40 +299,19 @@ resizing. `resize_libraries` defaults to all of the liberty libraries
272299
that have been read. Some designs have multiple libraries with
273300
different transistor thresholds (Vt) and are used to trade off power
274301
and speed. Chosing a low Vt library uses more power but results in a
275-
faster design after the resizing step. Use the `-dont_use` option to
276-
specify a list of patterns of cells to not use or the value returned
277-
by `get_lib_cells`. For example, `DLY*` says do not use cells with
278-
names that begin with `DLY` in all libraries.
279-
280-
```
281-
repair_max_cap -buffer_cell buffer_cell
282-
[-max_utilization util]
283-
repair_max_slew -buffer_cell buffer_cell
284-
[-max_utilization util]
285-
```
286-
The `repair_max_cap` and `repair_max_slew` commands repair nets with
287-
maximum capacitance or slew violations by inserting buffers in the
288-
net.
302+
faster design after the resizing step.
289303

290304
```
291-
repair_max_fanout -max_fanout fanout
292-
-buffer_cell buffer_cell
293-
[-max_utilization util]
294-
```
295-
The `repair_max_fanout` command repairs nets with a fanout greater
296-
than `fanout` by inserting buffers between the driver and the loads.
297-
Buffers are located at the center of each group of loads.
298-
299-
```
300-
repair_tie_fanout [-max_fanout fanout]
305+
repair_tie_fanout [-separation dist]
301306
[-verbose]
302307
lib_port
303308
```
304-
The `repair_tie_fanout` command repairs tie high/low nets with fanout
305-
greater than `fanout` by cloning the tie high/low driver.
306-
`lib_port` is the tie high/low port, which can be a library/cell/port
307-
name or object returned by `get_lib_pins`. Clones are located at the
308-
center of each group of loads.
309+
310+
The `repair_tie_fanout` command connects each tie high/low load to a
311+
copy of the tie high/low cell. `lib_port` is the tie high/low port,
312+
which can be a library/cell/port name or object returned by
313+
`get_lib_pins`. The tie high/low instance is separaated from the load
314+
by `dist` (in liberty units, typically microns).
309315

310316
```
311317
repair_hold_violations -buffer_cell buffer_cell
@@ -339,13 +345,12 @@ set_wire_rc -layer metal2
339345
340346
set buffer_cell BUF_X4
341347
set_dont_use {CLKBUF_* AOI211_X1 OAI211_X1}
342-
resize
348+
343349
buffer_ports -buffer_cell $buffer_cell
344-
repair_max_cap -buffer_cell $buffer_cell
345-
repair_max_slew -buffer_cell $buffer_cell
346-
repair_max_fanout -max_fanout 100 -buffer_cell $buffer_cell
347-
repair_tie_fanout -max_fanout 100 LOGIC0_X1/Z
348-
repair_tie_fanout -max_fanout 100 LOGIC1_X1/Z
350+
repair_design -max_wire_length 100 -buffer_cell $buffer_cell
351+
resize
352+
repair_tie_fanout LOGIC0_X1/Z
353+
repair_tie_fanout LOGIC1_X1/Z
349354
repair_hold_violations -buffer_cell $buffer_cell
350355
resize
351356
```
@@ -482,28 +487,28 @@ clock_tree_synthesis -buf_list <list_of_buffers> \
482487
[-wire_unit <wire_unit>] \
483488
[-clk_nets <list_of_clk_nets>] \
484489
[-out_path <lut_path>] \
485-
[-only_characterization <enable>]
490+
[-characterization_only]
486491
```
487492

488-
- ```buf_list``` (mandatory) are the master cells (buffers) that will be considered when making the wire segments.
489-
- ``sqr_cap`` (mandatory) is the capacitance (in picofarad) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments.
490-
- ``sqr_res`` (mandatory) is the resistance (in ohm) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments.
491-
- ``root_buffer`` (optional) is the master cell of the buffer that serves as root for the clock tree.
492-
If this parameter is omitted, the first master cell from ```buf_list``` is taken.
493-
- ``max_slew`` (optional) is the max slew value (in seconds) that the characterization will test.
493+
- ``-buf_list`` are the master cells (buffers) that will be considered when making the wire segments.
494+
- ``-sqr_cap`` is the capacitance (in picofarad) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments.
495+
- ``-sqr_res`` is the resistance (in ohm) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments.
496+
- ``-root_buffer`` is the master cell of the buffer that serves as root for the clock tree.
497+
If this parameter is omitted, the first master cell from ``-buf_list`` is taken.
498+
- ``-max_slew`` is the max slew value (in seconds) that the characterization will test.
494499
If this parameter is omitted, the code tries to obtain the value from the liberty file.
495-
- ``max_cap`` (optional) is the max capacitance value (in farad) that the characterization will test.
500+
- ``-max_cap`` is the max capacitance value (in farad) that the characterization will test.
496501
If this parameter is omitted, the code tries to obtain the value from the liberty file.
497-
- ``slew_inter`` (optional) is the time value (in seconds) that the characterization will consider for results.
502+
- ``-slew_inter`` is the time value (in seconds) that the characterization will consider for results.
498503
If this parameter is omitted, the code gets the default value (5.0e-12). Be careful that this value can be quite low for bigger technologies (>65nm).
499-
- ``cap_inter`` (optional) is the capacitance value (in farad) that the characterization will consider for results.
504+
- ``-cap_inter`` is the capacitance value (in farad) that the characterization will consider for results.
500505
If this parameter is omitted, the code gets the default value (5.0e-15). Be careful that this value can be quite low for bigger technologies (>65nm).
501-
- ``wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire.
502-
If this parameter is omitted, the code gets the value from ten times the height of ``root_buffer``.
503-
- ``clk_nets`` (optional) is a string containing the names of the clock roots.
506+
- ``-wire_unit`` is the minimum unit distance between buffers for a specific wire.
507+
If this parameter is omitted, the code gets the value from ten times the height of ``-root_buffer``.
508+
- ``-clk_nets`` is a string containing the names of the clock roots.
504509
If this parameter is omitted, TritonCTS looks for the clock roots automatically.
505-
- ``out_path`` (optional) is the output path (full) that the lut.txt and sol_list.txt files will be saved. This is used to load an existing characterization, without creating one from scratch.
506-
- ``only_characterization`` (optional), if true, makes so that the code exits after running the characterization.
510+
- ``-out_path`` is the output path (full) that the lut.txt and sol_list.txt files will be saved. This is used to load an existing characterization, without creating one from scratch.
511+
- ``-only_characterization`` is a flag that, when specified, makes so that only the library characterization step is run and no clock tree is inserted in the design.
507512

508513
Instead of creating a characterization, you can use use the following parameters to load a characterization file.
509514

@@ -514,16 +519,40 @@ clock_tree_synthesis -lut_file <lut_file> \
514519
[-wire_unit <wire_unit>] \
515520
[-clk_nets <list_of_clk_nets>]
516521
```
517-
- ```lut_file``` (mandatory) is the file containing delay, power and other metrics for each segment.
518-
- ``sol_list`` (mandatory) is the file containing the information on the topology of each segment (wirelengths and buffer masters).
519-
- ``sqr_res`` (mandatory) is the resistance (in ohm) per database units to be used in the wire segments.
520-
- ``root_buffer`` (mandatory) is the master cell of the buffer that serves as root for the clock tree.
521-
If this parameter is omitted, you can use the ```buf_list``` argument, using the first master cell. If both arguments are omitted, an error is raised.
522-
- ``wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire, based on your ```lut_file```.
523-
If this parameter is omitted, the code gets the value from the header of the ```lut_file```. For the old technology characterization, described [here](https://github.com/The-OpenROAD-Project/TritonCTS/blob/master/doc/Technology_characterization.md), this argument is mandatory, and omitting it raises an error.
524-
- ``clk_nets`` (optional) is a string containing the names of the clock roots.
522+
523+
- ``-lut_file`` (mandatory) is the file containing delay, power and other metrics for each segment.
524+
- ``-sol_list`` (mandatory) is the file containing the information on the topology of each segment (wirelengths and buffer masters).
525+
- ``-sqr_res`` (mandatory) is the resistance (in ohm) per database units to be used in the wire segments.
526+
- ``-root_buffer`` (mandatory) is the master cell of the buffer that serves as root for the clock tree.
527+
If this parameter is omitted, you can use the ``-buf_list`` argument, using the first master cell. If both arguments are omitted, an error is raised.
528+
- ``-wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire, based on your ``-lut_file``.
529+
If this parameter is omitted, the code gets the value from the header of the ``-lut_file``. For the old technology characterization, described [here](https://github.com/The-OpenROAD-Project/TritonCTS/blob/master/doc/Technology_characterization.md), this argument is mandatory, and omitting it raises an error.
530+
- ``-clk_nets`` (optional) is a string containing the names of the clock roots.
525531
If this parameter is omitted, TritonCTS looks for the clock roots automatically.
526532

533+
Another command available from TritonCTS is ``report_cts``. It is used to extract metrics after a successful ``clock_tree_synthesis`` run. These are: Number of Clock Roots, Number of Buffers Inserted, Number of Clock Subnets, and Number of Sinks.
534+
535+
```
536+
read_lef "mylef.lef"
537+
read_liberty "myliberty.lib"
538+
read_def "mydef.def"
539+
read_verilog "myverilog.v"
540+
read_sdc "mysdc.sdc"
541+
542+
report_checks
543+
544+
clock_tree_synthesis -lut_file "lut.txt" \
545+
-sol_list "sol_list.txt" \
546+
-root_buf "BUF_X4" \
547+
-wire_unit 20
548+
549+
report_cts [-out_file "file.txt"]
550+
```
551+
552+
- ``-out_file`` (optional) is the file containing the TritonCTS reports.
553+
If this parameter is omitted, the metrics are shown on the standard output.
554+
555+
527556
#### Global Routing
528557

529558
FastRoute global route.

include/openroad/OpenRoad.hh

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,11 @@ namespace pdnsim {
9898
class PDNSim;
9999
}
100100

101+
namespace antenna_checker {
102+
class AntennaChecker;
103+
}
104+
105+
101106
namespace ord {
102107

103108
using std::string;
@@ -128,6 +133,7 @@ public:
128133
replace::Replace* getReplace() { return replace_; }
129134
pdnsim::PDNSim* getPDNSim() { return pdnsim_; }
130135
FastRoute::FastRouteKernel* getFastRoute() { return fastRoute_; }
136+
antenna_checker::AntennaChecker *getAntennaChecker(){ return antennaChecker_; }
131137
// Return the bounding box of the db rows.
132138
odb::Rect getCore();
133139
// Return true if the command units have been initialized.
@@ -186,6 +192,7 @@ private:
186192
TritonCTS::TritonCTSKernel *tritonCts_;
187193
tapcell::Tapcell *tapcell_;
188194
OpenRCX::Ext *extractor_;
195+
antenna_checker::AntennaChecker *antennaChecker_;
189196
#ifdef BUILD_OPENPHYSYN
190197
psn::Psn *psn_;
191198
#endif
@@ -206,5 +213,9 @@ getCore(odb::dbBlock *block);
206213
odb::Point
207214
closestPtInRect(odb::Rect rect,
208215
odb::Point pt);
216+
odb::Point
217+
closestPtInRect(odb::Rect rect,
218+
int x,
219+
int y);
209220

210221
} // namespace

src/CMakeLists.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ set(OPENRCX_HOME ${OPENROAD_HOME}/src/OpenRCX)
3030
set(MPLACE_HOME ${PROJECT_SOURCE_DIR}/src/TritonMacroPlace)
3131
set(OPENPHYSYN_HOME ${PROJECT_SOURCE_DIR}/src/OpenPhySyn)
3232
set(PDNSIM_HOME ${PROJECT_SOURCE_DIR}/src/PDNSim)
33+
set(ANTENNACHECKER_HOME ${PROJECT_SOURCE_DIR}/src/antennachecker)
3334

3435
set(OPENROAD_TCL_INIT ${CMAKE_CURRENT_BINARY_DIR}/OpenRoadTclInitVar.cc)
3536

@@ -220,6 +221,7 @@ add_subdirectory(tapcell)
220221
add_subdirectory(TritonMacroPlace)
221222
add_subdirectory(OpenRCX)
222223
add_subdirectory(PDNSim)
224+
add_subdirectory(antennachecker)
223225

224226
if(BUILD_OPENPHYSYN)
225227
add_subdirectory(OpenPhySyn)
@@ -255,6 +257,7 @@ target_include_directories(openroad
255257
${TAPCELL_HOME}/include
256258
${OPENRCX_HOME}/include
257259
${PDNSIM_HOME}/include
260+
${ANTENNACHECKER_HOME}/include
258261
${TCL_INCLUDE_PATH}
259262
${Boost_INCLUDE_DIRS}
260263
)
@@ -285,6 +288,7 @@ target_link_libraries(openroad
285288
defout
286289
lefin
287290
lefout
291+
antennachecker
288292
zutil
289293
${TCL_LIBRARY}
290294
)

src/FastRoute

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