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-```buf_list``` (mandatory) are the master cells (buffers) that will be considered when making the wire segments.
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-``sqr_cap`` (mandatory) is the capacitance (in picofarad) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments.
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-``sqr_res`` (mandatory) is the resistance (in ohm) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments.
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-``root_buffer`` (optional) is the master cell of the buffer that serves as root for the clock tree.
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If this parameter is omitted, the first master cell from ```buf_list``` is taken.
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-``max_slew`` (optional) is the max slew value (in seconds) that the characterization will test.
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-``-buf_list`` are the master cells (buffers) that will be considered when making the wire segments.
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-``-sqr_cap`` is the capacitance (in picofarad) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments.
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-``-sqr_res`` is the resistance (in ohm) per micrometer (thus, the same unit that is used in the LEF syntax) to be used in the wire segments.
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-``-root_buffer`` is the master cell of the buffer that serves as root for the clock tree.
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If this parameter is omitted, the first master cell from ``-buf_list`` is taken.
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-``-max_slew`` is the max slew value (in seconds) that the characterization will test.
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If this parameter is omitted, the code tries to obtain the value from the liberty file.
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-``max_cap`` (optional) is the max capacitance value (in farad) that the characterization will test.
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-``-max_cap`` is the max capacitance value (in farad) that the characterization will test.
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If this parameter is omitted, the code tries to obtain the value from the liberty file.
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-``slew_inter`` (optional) is the time value (in seconds) that the characterization will consider for results.
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-``-slew_inter`` is the time value (in seconds) that the characterization will consider for results.
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If this parameter is omitted, the code gets the default value (5.0e-12). Be careful that this value can be quite low for bigger technologies (>65nm).
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-``cap_inter`` (optional) is the capacitance value (in farad) that the characterization will consider for results.
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-``-cap_inter`` is the capacitance value (in farad) that the characterization will consider for results.
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If this parameter is omitted, the code gets the default value (5.0e-15). Be careful that this value can be quite low for bigger technologies (>65nm).
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-``wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire.
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If this parameter is omitted, the code gets the value from ten times the height of ``root_buffer``.
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-``clk_nets`` (optional) is a string containing the names of the clock roots.
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-``-wire_unit`` is the minimum unit distance between buffers for a specific wire.
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If this parameter is omitted, the code gets the value from ten times the height of ``-root_buffer``.
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-``-clk_nets`` is a string containing the names of the clock roots.
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If this parameter is omitted, TritonCTS looks for the clock roots automatically.
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-``out_path`` (optional) is the output path (full) that the lut.txt and sol_list.txt files will be saved. This is used to load an existing characterization, without creating one from scratch.
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-``only_characterization``(optional), if true, makes so that the code exits after running the characterization.
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-``-out_path`` is the output path (full) that the lut.txt and sol_list.txt files will be saved. This is used to load an existing characterization, without creating one from scratch.
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-``-only_characterization``is a flag that, when specified, makes so that only the library characterization step is run and no clock tree is inserted in the design.
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Instead of creating a characterization, you can use use the following parameters to load a characterization file.
-```lut_file``` (mandatory) is the file containing delay, power and other metrics for each segment.
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-``sol_list`` (mandatory) is the file containing the information on the topology of each segment (wirelengths and buffer masters).
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-``sqr_res`` (mandatory) is the resistance (in ohm) per database units to be used in the wire segments.
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-``root_buffer`` (mandatory) is the master cell of the buffer that serves as root for the clock tree.
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If this parameter is omitted, you can use the ```buf_list``` argument, using the first master cell. If both arguments are omitted, an error is raised.
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-``wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire, based on your ```lut_file```.
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If this parameter is omitted, the code gets the value from the header of the ```lut_file```. For the old technology characterization, described [here](https://github.com/The-OpenROAD-Project/TritonCTS/blob/master/doc/Technology_characterization.md), this argument is mandatory, and omitting it raises an error.
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-``clk_nets`` (optional) is a string containing the names of the clock roots.
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-``-lut_file`` (mandatory) is the file containing delay, power and other metrics for each segment.
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-``-sol_list`` (mandatory) is the file containing the information on the topology of each segment (wirelengths and buffer masters).
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-``-sqr_res`` (mandatory) is the resistance (in ohm) per database units to be used in the wire segments.
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-``-root_buffer`` (mandatory) is the master cell of the buffer that serves as root for the clock tree.
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If this parameter is omitted, you can use the ``-buf_list`` argument, using the first master cell. If both arguments are omitted, an error is raised.
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-``-wire_unit`` (optional) is the minimum unit distance between buffers for a specific wire, based on your ``-lut_file``.
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If this parameter is omitted, the code gets the value from the header of the ``-lut_file``. For the old technology characterization, described [here](https://github.com/The-OpenROAD-Project/TritonCTS/blob/master/doc/Technology_characterization.md), this argument is mandatory, and omitting it raises an error.
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-``-clk_nets`` (optional) is a string containing the names of the clock roots.
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If this parameter is omitted, TritonCTS looks for the clock roots automatically.
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Another command available from TritonCTS is ``report_cts``. It is used to extract metrics after a successful ``clock_tree_synthesis`` run. These are: Number of Clock Roots, Number of Buffers Inserted, Number of Clock Subnets, and Number of Sinks.
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```
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read_lef "mylef.lef"
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read_liberty "myliberty.lib"
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read_def "mydef.def"
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read_verilog "myverilog.v"
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read_sdc "mysdc.sdc"
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report_checks
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clock_tree_synthesis -lut_file "lut.txt" \
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-sol_list "sol_list.txt" \
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-root_buf "BUF_X4" \
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-wire_unit 20
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report_cts [-out_file "file.txt"]
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```
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-``-out_file`` (optional) is the file containing the TritonCTS reports.
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If this parameter is omitted, the metrics are shown on the standard output.
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