Merge branch 'The-OpenROAD-Project:master' into master

Author: shypark98

BUILD.bazel

@@ -142,7 +142,7 @@ cc_binary(
     deps = [
         ":openroad_lib",
         ":openroad_version",
-        "//:ord",
+        ":ord",
         "//src/cut",
         "//src/gui",
         "//src/sta:opensta_lib",

src/cgt/include/cgt/ClockGating.h

@@ -143,8 +143,8 @@ class ClockGating
   // Helper for inserting new instances/nets into a network.
   NetworkBuilder network_builder_;
 
-  Logger* logger_;
-  sta::dbSta* sta_;
+  Logger* logger_ = nullptr;
+  sta::dbSta* sta_ = nullptr;
   std::unique_ptr<cut::AbcLibraryFactory> abc_factory_;
   std::unique_ptr<cut::AbcLibrary> abc_library_;
 };

src/cgt/src/ClockGating.cpp

@@ -375,13 +375,6 @@ void ClockGating::run()
   abc_factory_->AddDbSta(sta_);
   abc_library_ = std::make_unique<cut::AbcLibrary>(abc_factory_->Build());
 
-  abc::Abc_SclInstallGenlib(abc_library_->abc_library(),
-                            /*Slew=*/0,
-                            /*Gain=*/0,
-                            /*fUseAll=*/0,
-                            /*nGatesMin=*/0);
-  abc::Mio_LibraryTransferCellIds();
-
   dump("pre");
 
   std::vector<sta::Instance*> instances;
@@ -519,7 +512,7 @@ void ClockGating::run()
         continue;
       }
 
-      correct_conds = gate_cond_cover;
+      correct_conds = std::move(gate_cond_cover);
       searchClockGates(instance,
                        correct_conds,
                        correct_conds.begin(),
@@ -664,10 +657,11 @@ void ClockGating::searchClockGates(sta::Instance* const instance,
                                    abc::Abc_Ntk_t& abc_network,
                                    const bool clk_enable)
 {
-  if (end - begin < 2) {
+  size_t half_len = (end - begin) / 2;
+  if (half_len == 0) {
     return;
   }
-  auto mid = begin + (end - begin) / 2;
+  auto mid = begin + half_len;
   auto combined_candidate_names
       = combinedGatingCondNames(sta_->getDbNetwork(), mid, end, clk_enable);
   debugPrint(
@@ -691,6 +685,7 @@ void ClockGating::searchClockGates(sta::Instance* const instance,
                "Clock gating signals: '{}' can be dropped",
                combined_candidate_names);
     good_gate_conds.erase(mid, end);
+    mid = begin + half_len;
   } else if (end - mid > 1) {
     debugPrint(logger_,
                CGT,
@@ -832,6 +827,8 @@ static abc::Abc_Obj_t* regDataFunctionToAbc(sta::dbNetwork* const network,
       case sta::FuncExpr::op_or:
       case sta::FuncExpr::op_xor:
         expr_stack.push_back(expr->right());
+        expr_stack.push_back(expr->left());
+        break;
       case sta::FuncExpr::op_not:
         expr_stack.push_back(expr->left());
         break;

src/cgt/test/aes_nangate45.ok

@@ -3,8 +3,6 @@
 [WARNING CUT-0021] Leakage power doesn't exist for cell LOGIC0_X1
 [WARNING CUT-0021] Leakage power doesn't exist for cell LOGIC1_X1
 Derived GENLIB library "NangateOpenCellLibrary" with 92 gates.
-Warning: Detected 2 multi-output gates (for example, "FA_X1").
-SC library cannot be found.
 [INFO CGT-0003] Clock gating instance 0/562
 [INFO CGT-0004] Accepted clock enable '_13148_ | _04712_ | _04712_ | _00499_ | _05106_ | _05208_' for instance dcnt\[0\]$_SDFFE_PN0P_
 [INFO CGT-0004] Accepted clock enable '_13151_ | _11055_ | _07150_ | _09231_ | _11144_ | _05152_ | _07152_ | _04670_' for instance ld_r$_DFF_P_

src/cgt/test/countdown_asap7.ok

@@ -11,8 +11,6 @@
 [INFO ODB-0227] LEF file: asap7/asap7_tech_1x_201209.lef, created 30 layers, 9 vias
 [INFO ODB-0227] LEF file: asap7/asap7sc7p5t_28_R_1x_220121a.lef, created 212 library cells
 Derived GENLIB library "asap7sc7p5t_AO_RVT_FF_nldm_211120" with 169 gates.
-Warning: Detected 2 multi-output gates (for example, "FAx1_ASAP7_75t_R").
-SC library cannot be found.
 [INFO CGT-0003] Clock gating instance 0/3
 [INFO CGT-0004] Accepted clock enable '_05_ | _02_ | _01_ | _10_ | _03_' for instance val\[0\]$_DFF_PP1_
 No differences found.

src/cgt/test/ibex_sky130hd.ok

@@ -1,8 +1,6 @@
 [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias
 [INFO ODB-0227] LEF file: sky130hd/sky130hd_std_cell.lef, created 437 library cells
 Derived GENLIB library "sky130_fd_sc_hd__ss_n40C_1v40" with 317 gates.
-Warning: Detected 9 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
-SC library cannot be found.
 [INFO CGT-0003] Clock gating instance 0/946
 [INFO CGT-0004] Accepted clock enable 'ex_block_i.gen_multdiv_fast.multdiv_i.md_state_q\[5\] | _03749_ | _03000_ | _04094_ | _03636_ | _04093_' for instance _20290_
 [INFO CGT-0004] Accepted clock enable 'cs_registers_i.mcountinhibit_q\[0\] | _05037_ | _04531_ | _04533_ | _04495_ | _04405_ | _05854_ | _04404_' for instance cs_registers_i.mcountinhibit_q\[0\]$_DFFE_PN0P_

src/cut/include/cut/logic_cut.h

@@ -6,8 +6,8 @@
 #include <utility>
 #include <vector>
 
-#include "abc_library_factory.h"
 #include "base/abc/abc.h"
+#include "cut/abc_library_factory.h"
 #include "db_sta/dbNetwork.hh"
 #include "sta/NetworkClass.hh"
 #include "utl/Logger.h"
@@ -18,9 +18,9 @@ namespace cut {
 class LogicCut
 {
  public:
-  LogicCut(std::vector<sta::Net*>& primary_inputs,
-           std::vector<sta::Net*>& primary_outputs,
-           sta::InstanceSet& cut_instances)
+  LogicCut(std::vector<sta::Net*>&& primary_inputs,
+           std::vector<sta::Net*>&& primary_outputs,
+           sta::InstanceSet&& cut_instances)
       : primary_inputs_(std::move(primary_inputs)),
         primary_outputs_(std::move(primary_outputs)),
         cut_instances_(std::move(cut_instances))

src/cut/include/cut/logic_extractor.h

@@ -6,9 +6,9 @@
 #include <unordered_set>
 #include <vector>
 
-#include "abc_library_factory.h"
+#include "cut/abc_library_factory.h"
+#include "cut/logic_cut.h"
 #include "db_sta/dbSta.hh"
-#include "logic_cut.h"
 #include "sta/Graph.hh"
 #include "sta/NetworkClass.hh"
 #include "sta/SearchPred.hh"

src/cut/src/blif.cpp

@@ -534,7 +534,7 @@ bool Blif::readBlif(const char* file_name, odb::dbBlock* block)
           auto port_ = network_->libertyPort(pin_);
           if (port_->isClock()) {
             mtermName = mTerm->getName();
-            netName = connection;
+            netName = std::move(connection);
             break;
           }
         }

src/cut/src/logic_extractor.cpp

@@ -385,7 +385,9 @@ LogicCut LogicExtractorFactory::BuildLogicCut(AbcLibrary& abc_network)
   std::vector<sta::Net*> primary_output_nets
       = ConvertIoPinsToNets(filtered_primary_outputs);
 
-  return LogicCut(primary_input_nets, primary_output_nets, cut_instances);
+  return LogicCut(std::move(primary_input_nets),
+                  std::move(primary_output_nets),
+                  std::move(cut_instances));
 }
 
 }  // namespace cut