rsz: Updated comment

jhkim-pii · jhkim-pii · commit 40209e7109ef · 2025-12-23T21:21:42.000+09:00
Signed-off-by: Jaehyun Kim &lt;jhkim@precisioninno.com&gt;
diff --git a/src/rsz/test/repair_clk_nets1.tcl b/src/rsz/test/repair_clk_nets1.tcl
@@ -21,7 +21,7 @@ foreach net_name {in1 n1 n2 out1} {
   [sta::sta_to_db_net [get_net $net_name]] setSigType CLOCK
 }
 
-# wire length = 1500u -> 2 buffers required
+# wire length = 1500u -> at least 2 buffers are required
 repair_clock_nets -max_wire_length 600
 
 puts "\n# All nets in the path should be CLOCK type."

Original file line number	Diff line number	Diff line change
`@@ -21,7 +21,7 @@ foreach net_name {in1 n1 n2 out1} {`
`21`	`21`	`[sta::sta_to_db_net [get_net $net_name]] setSigType CLOCK`
`22`	`22`	`}`
`23`	`23`
`24`		`-# wire length = 1500u -> 2 buffers required`
	`24`	`+# wire length = 1500u -> at least 2 buffers are required`
`25`	`25`	`repair_clock_nets -max_wire_length 600`
`26`	`26`
`27`	`27`	`puts "\n# All nets in the path should be CLOCK type."`