Fixed DbInstanceNetIterator to iterate both flat and hierarchical nets within the given instance.

- Moved dbSta/test/get_ports2* test cases to rsz/test/buffer_ports11* test cases.

Signed-off-by: Jaehyun Kim <[email protected]>

Author: jhkim-pii

src/cts/test/hier_insertion_delay.vok

@@ -1,6 +1,43 @@
 module multi_sink (clk);
  input clk;
 
+ wire clknet_leaf_15_clk_regs;
+ wire clknet_leaf_13_clk_regs;
+ wire clknet_leaf_12_clk_regs;
+ wire clknet_leaf_11_clk_regs;
+ wire clk_regs;
+ wire clknet_0_clk;
+ wire clknet_1_0__leaf_clk;
+ wire clknet_leaf_0_clk_regs;
+ wire clknet_leaf_1_clk_regs;
+ wire clknet_leaf_2_clk_regs;
+ wire clknet_leaf_3_clk_regs;
+ wire clknet_leaf_4_clk_regs;
+ wire clknet_leaf_5_clk_regs;
+ wire clknet_leaf_6_clk_regs;
+ wire clknet_leaf_7_clk_regs;
+ wire clknet_leaf_8_clk_regs;
+ wire clknet_leaf_9_clk_regs;
+ wire clknet_leaf_10_clk_regs;
+ wire clknet_leaf_14_clk_regs;
+ wire clknet_leaf_16_clk_regs;
+ wire clknet_leaf_17_clk_regs;
+ wire clknet_leaf_18_clk_regs;
+ wire clknet_leaf_19_clk_regs;
+ wire clknet_leaf_20_clk_regs;
+ wire clknet_leaf_21_clk_regs;
+ wire clknet_leaf_22_clk_regs;
+ wire clknet_leaf_23_clk_regs;
+ wire clknet_leaf_24_clk_regs;
+ wire clknet_leaf_25_clk_regs;
+ wire clknet_leaf_26_clk_regs;
+ wire clknet_leaf_27_clk_regs;
+ wire clknet_0_clk_regs;
+ wire clknet_1_0__leaf_clk_regs;
+ wire clknet_1_1__leaf_clk_regs;
+ wire delaynet_0_core;
+ wire delaynet_1_core;
+ wire delaynet_2_core;
 
  CLKBUF_X3 delaybuf_2_core (.A(delaynet_2_core),
     .Z(clknet_0_clk));

src/cts/test/simple_test_hier_out.vok

@@ -1,6 +1,9 @@
 module test_16_sinks (clk);
  input clk;
 
+ wire clknet_1_1__leaf_clk;
+ wire clknet_1_0__leaf_clk;
+ wire clknet_0_clk;
 
  INV_X1 clkload0 (.A(clknet_1_1__leaf_clk));
  CLKBUF_X3 clkbuf_1_1__f_clk (.A(clknet_0_clk),

src/dbSta/src/dbNetwork.cc

@@ -312,23 +312,81 @@ class DbInstanceNetIterator : public InstanceNetIterator
   dbSet<dbNet>::iterator end_;
   dbSet<dbModNet>::iterator mod_net_iter_;
   dbSet<dbModNet>::iterator mod_net_end_;
+  std::vector<dbNet*> flat_nets_vec_;
+  size_t flat_net_idx_ = 0;
 };
 
 DbInstanceNetIterator::DbInstanceNetIterator(const Instance* instance,
                                              const dbNetwork* network)
     : network_(network)
 {
   if (network_->hasHierarchy()) {
-    dbInst* db_inst;
-    dbModInst* mod_inst;
-    network_->staToDb(instance, db_inst, mod_inst);
-    if (mod_inst) {
-      dbModule* master = mod_inst->getMaster();
-      dbSet<dbModNet> nets = master->getModNets();
-      mod_net_iter_ = nets.begin();
-      mod_net_end_ = nets.end();
+    //
+    // In hierarchical flow, the net iterator collects both hierarchical
+    // nets (dbModNets) and unique flat nets (dbNets) within the
+    // instance's module scope.
+    // Flat nets can be retrieved by traversing instance ITerms and BTerms.
+    // Avoids the duplication b/w flat and hierarchical nets.
+    //
+
+    // Get the module of the instance
+    dbModule* module = nullptr;
+    if (instance == network->topInstance()) {
+      module = network->block()->getTopModule();
+    } else {
+      dbInst* db_inst;
+      dbModInst* mod_inst;
+      network_->staToDb(instance, db_inst, mod_inst);
+      if (mod_inst) {
+        module = mod_inst->getMaster();
+      }
+    }
+
+    if (module) {
+      // Get dbModNets
+      dbSet<dbModNet> mod_nets = module->getModNets();
+      mod_net_iter_ = mod_nets.begin();
+      mod_net_end_ = mod_nets.end();
+
+      // Keep track of flat nets that are already represented by a mod_net
+      // to avoid returning both.
+      std::set<dbNet*> handled_flat_nets;
+      for (dbModNet* mod_net : mod_nets) {
+        dbNet* flat_net = network_->findRelatedDbNet(mod_net);
+        if (flat_net) {
+          handled_flat_nets.insert(flat_net);
+        }
+      }
+
+      // Collect dbNets from children dbInsts' pins that are not already
+      // handled.
+      std::set<dbNet*> flat_nets_set;
+      for (dbInst* child_inst : module->getInsts()) {
+        for (dbITerm* iterm : child_inst->getITerms()) {
+          dbNet* flat_net = iterm->getNet();
+          if (flat_net
+              && handled_flat_nets.find(flat_net) == handled_flat_nets.end()) {
+            flat_nets_set.insert(flat_net);
+          }
+        }
+      }
+
+      // For top instance, also check top-level ports (BTerms)
+      if (instance == network->topInstance()) {
+        for (dbBTerm* bterm : network->block()->getBTerms()) {
+          dbNet* flat_net = bterm->getNet();
+          if (flat_net
+              && handled_flat_nets.find(flat_net) == handled_flat_nets.end()) {
+            flat_nets_set.insert(flat_net);
+          }
+        }
+      }
+      flat_nets_vec_.assign(flat_nets_set.begin(), flat_nets_set.end());
     }
   } else {
+    //
+    // In flat flow, the net iterator collects all nets from top block
+    //
     if (instance == network->topInstance()) {
       dbSet<dbNet> nets = network->block()->getNets();
       iter_ = nets.begin();
@@ -340,17 +398,27 @@ DbInstanceNetIterator::DbInstanceNetIterator(const Instance* instance,
 bool DbInstanceNetIterator::hasNext()
 {
   if (network_->hasHierarchy()) {
-    return mod_net_iter_ != mod_net_end_;
+    if (mod_net_iter_ != mod_net_end_) {
+      return true;
+    }
+    return flat_net_idx_ < flat_nets_vec_.size();
   }
   return iter_ != end_;
 }
 
 Net* DbInstanceNetIterator::next()
 {
   if (network_->hasHierarchy()) {
-    dbModNet* net = *mod_net_iter_;
-    mod_net_iter_++;
-    return network_->dbToSta(net);
+    if (mod_net_iter_ != mod_net_end_) {
+      dbModNet* net = *mod_net_iter_;
+      mod_net_iter_++;
+      return network_->dbToSta(net);
+    }
+    if (flat_net_idx_ < flat_nets_vec_.size()) {
+      dbNet* net = flat_nets_vec_[flat_net_idx_++];
+      return network_->dbToSta(net);
+    }
+    return nullptr;
   }
   dbNet* net = *iter_;
   iter_++;

src/dbSta/test/BUILD

@@ -12,8 +12,6 @@ COMPULSORY_TESTS = [
     "find_clks2",
     "get_ports1",
     "get_ports1_hier",
-    "get_ports2",
-    "get_ports2_hier",
     "hier2",
     "hierclock",
     "hierwrite",
@@ -116,7 +114,6 @@ filegroup(
         "example1_slow.lib",
         "example1_typ.lib",
         "get_ports1.v",
-        "get_ports2.v",
         "helpers.tcl",
         "hier1.def",
         "hier1.sdc",

src/dbSta/test/CMakeLists.txt

@@ -9,8 +9,6 @@ or_integration_tests(
     find_clks2
     get_ports1
     get_ports1_hier
-    get_ports2
-    get_ports2_hier
     hier2
     hierclock
     hierwrite

src/dbSta/test/hier2_out.vok

@@ -5,6 +5,7 @@ module top (a,
  input b;
  output out;
 
+ wire a_int;
 
  INV_X1 _4_ (.ZN(a_int),
     .A(a));

src/dbSta/test/hierclock_out.vok

@@ -19,6 +19,8 @@ module hierclock (a_count_valid_o,
  output [3:0] b_count_o;
  input [3:0] b_i;
 
+ wire clk2_int;
+ wire clk1_int;
 
  clockgen U1 (.clk_i(clk_i),
     .rst_n_i(rst_n_i),
@@ -58,6 +60,19 @@ module clockgen (clk_i,
  output clk1_o;
  output clk2_o;
 
+ wire _03_;
+ wire _04_;
+ wire _05_;
+ wire _06_;
+ wire _11_;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _19_;
+ wire _20_;
+ wire _21_;
+ wire _22_;
  wire [3:0] counter_q;
 
  INV_X1 _28_ (.A(rst_n_i),
@@ -124,6 +139,27 @@ module counter (clk_i,
  output count_valid_o;
 
  wire count_valid_q;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
  wire [3:0] counter_q;
 
  INV_X1 _49_ (.A(_41_),
@@ -217,6 +253,27 @@ module counter_U3 (clk_i,
  output count_valid_o;
 
  wire count_valid_q;
+ wire _12_;
+ wire _13_;
+ wire _14_;
+ wire _15_;
+ wire _16_;
+ wire _26_;
+ wire _27_;
+ wire _28_;
+ wire _29_;
+ wire _30_;
+ wire _31_;
+ wire _32_;
+ wire _33_;
+ wire _34_;
+ wire _35_;
+ wire _36_;
+ wire _38_;
+ wire _39_;
+ wire _40_;
+ wire _41_;
+ wire _42_;
  wire [3:0] counter_q;
 
  INV_X1 _49_ (.A(_41_),