Merge remote-tracking branch 'origin/master' into HEAD

Author: oharboe

MODULE.bazel

@@ -162,7 +162,7 @@ bazel_dep(name = "bazel-orfs")
 # To bump version, run: bazelisk run @bazel-orfs//:bump
 git_override(
     module_name = "bazel-orfs",
-    commit = "3c59a8ef8a1b4cc4962ebcb7bb3f09102c288ec5",
+    commit = "06be7f48c85f3e66e4a79205a68ae2170be88273",
     remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git",
 )
 
@@ -171,10 +171,10 @@ orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories")
 # To bump version, run: bazelisk run @bazel-orfs//:bump
 orfs.default(
     # Official image https://hub.docker.com/r/openroad/orfs/tags
-    image = "docker.io/openroad/orfs:v3.0-4226-ga3914fbf6",
+    image = "docker.io/openroad/orfs:v3.0-4230-g26b521c49",
     # Use OpenROAD of this repo instead of from the docker image
     openroad = "//:openroad",
-    sha256 = "ff09cbf243d07481643109a583f4f9547e74f95a06f55cb9af446612a6eb7033",
+    sha256 = "8fc7ac130828053d7f0a9ad93ae8e3a74e9b24be6e76f9900f809ff93a80d005",
 )
 use_repo(orfs, "com_github_nixos_patchelf_download")
 use_repo(orfs, "docker_orfs")

MODULE.bazel.lock

@@ -3,6 +3,7 @@
 
 #include "ord/Design.h"
 
+#include <algorithm>
 #include <cmath>
 #include <cstdint>
 #include <istream>
@@ -224,7 +225,7 @@ std::uint64_t Design::getNetRoutedLength(odb::dbNet* net)
     for (odb::dbSWire* swire : net->getSWires()) {
       for (odb::dbSBox* wire : swire->getWires()) {
         if (wire != nullptr && !(wire->isVia())) {
-          route_length += wire->getLength();
+          route_length += std::max(wire->getDX(), wire->getDY());
         }
       }
     }

src/Design.cc

@@ -188,8 +188,8 @@ class TritonCTS
   double computeInsertionDelay(const std::string& name,
                                odb::dbInst* inst,
                                odb::dbMTerm* mterm);
-  void writeDummyLoadsToDb(Clock& clockNet,
-                           std::unordered_set<odb::dbInst*>& dummies);
+  int writeDummyLoadsToDb(Clock& clockNet,
+                          std::unordered_set<odb::dbInst*>& dummies);
   bool computeIdealOutputCaps(Clock& clockNet);
   void findCandidateDummyCells(std::vector<sta::LibertyCell*>& dummyCandidates);
   odb::dbInst* insertDummyCell(

src/cts/include/cts/TritonCTS.h

@@ -221,6 +221,8 @@ class TreeBuilder
 
   float getAveSinkArrival() const { return aveArrival_; }
   void setAveSinkArrival(float arrival) { aveArrival_ = arrival; }
+  float getNDummies() const { return nDummies_; }
+  void setNDummies(float nDummies) { nDummies_ = nDummies; }
   odb::dbInst* getTopBuffer() const { return topBuffer_; }
   void setTopBuffer(odb::dbInst* inst) { topBuffer_ = inst; }
   std::string getTopBufferName() const { return topBufferName_; }
@@ -256,6 +258,7 @@ class TreeBuilder
       insertionDelays_;
   TreeType type_ = TreeType::RegularTree;
   float aveArrival_ = 0.0;
+  int nDummies_ = 0;
   odb::dbInst* topBuffer_ = nullptr;
   std::string topBufferName_;
   odb::dbNet* drivingNet_ = nullptr;

src/cts/src/TreeBuilder.h

@@ -494,7 +494,8 @@ void TritonCTS::writeDataToDb()
       writeClockNDRsToDb(builder.get());
     }
     if (options_->dummyLoadEnabled()) {
-      writeDummyLoadsToDb(builder->getClock(), clkDummies);
+      int nDummies = writeDummyLoadsToDb(builder->getClock(), clkDummies);
+      builder->setNDummies(nDummies);
     }
   }
 
@@ -538,7 +539,8 @@ void TritonCTS::writeDataToDb()
       }
       logger_->info(CTS, 102, " Path depth {} - {}", minDepth, maxDepth);
       if (options_->dummyLoadEnabled()) {
-        logger_->info(CTS, 207, " Leaf load cells {}", dummyLoadIndex_);
+        logger_->info(
+            CTS, 207, " Dummy loads inserted {}", builder->getNDummies());
       }
     }
   }
@@ -2122,20 +2124,21 @@ sta::LibertyCell* findBestDummyCell(
   return bestCell;
 }
 
-void TritonCTS::writeDummyLoadsToDb(Clock& clockNet,
-                                    std::unordered_set<odb::dbInst*>& dummies)
+int TritonCTS::writeDummyLoadsToDb(Clock& clockNet,
+                                   std::unordered_set<odb::dbInst*>& dummies)
 {
   // Traverse clock tree and compute ideal output caps for clock
   // buffers in the same level
   if (!computeIdealOutputCaps(clockNet)) {
     // No cap adjustment is needed
-    return;
+    return 0;
   }
 
   // Find suitable candidate cells for dummy loads
   std::vector<sta::LibertyCell*> dummyCandidates;
   findCandidateDummyCells(dummyCandidates);
 
+  int nDummies = 0;
   clockNet.forEachSubNet([&](ClockSubNet& subNet) {
     subNet.forEachSink([&](ClockInst* inst) {
       if (inst->isClockBuffer()
@@ -2145,6 +2148,7 @@ void TritonCTS::writeDummyLoadsToDb(Clock& clockNet,
             = insertDummyCell(clockNet, inst, dummyCandidates);
         if (dummyInst != nullptr) {
           dummies.insert(dummyInst);
+          nDummies++;
         }
       }
     });
@@ -2153,6 +2157,7 @@ void TritonCTS::writeDummyLoadsToDb(Clock& clockNet,
   if (logger_->debugCheck(utl::CTS, "dummy load", 1)) {
     printClockNetwork(clockNet);
   }
+  return nDummies;
 }
 
 // Return true if any clock buffers need cap adjustment; false otherwise

src/cts/src/TritonCTS.cpp

@@ -103,13 +103,13 @@
 [INFO CTS-0100]  Leaf buffers 103
 [INFO CTS-0101]  Average sink wire length 9313.40 um
 [INFO CTS-0102]  Path depth 16 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 2254
 [INFO CTS-0100]  Leaf buffers 227
 [INFO CTS-0101]  Average sink wire length 4121.94 um
 [INFO CTS-0102]  Path depth 17 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 [INFO CTS-0033] Balancing latency for clock clk
 [INFO CTS-0036]  inserted 3 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 3

src/cts/test/array.ok

@@ -103,13 +103,13 @@
 [INFO CTS-0100]  Leaf buffers 103
 [INFO CTS-0101]  Average sink wire length 9313.40 um
 [INFO CTS-0102]  Path depth 16 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 2254
 [INFO CTS-0100]  Leaf buffers 227
 [INFO CTS-0101]  Average sink wire length 4121.94 um
 [INFO CTS-0102]  Path depth 17 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 [INFO CTS-0033] Balancing latency for clock clk
 [INFO CTS-0036]  inserted 3 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 3

src/cts/test/array_ins_delay.ok

@@ -102,13 +102,13 @@
 [INFO CTS-0100]  Leaf buffers 103
 [INFO CTS-0101]  Average sink wire length 9415.86 um
 [INFO CTS-0102]  Path depth 16 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 2254
 [INFO CTS-0100]  Leaf buffers 227
 [INFO CTS-0101]  Average sink wire length 4117.74 um
 [INFO CTS-0102]  Path depth 17 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 [INFO CTS-0033] Balancing latency for clock clk
 [INFO CTS-0036]  inserted 4 delay buffers
 [INFO CTS-0037] Total number of delay buffers: 4

src/cts/test/array_no_blockages.ok

@@ -103,13 +103,13 @@
 [INFO CTS-0100]  Leaf buffers 103
 [INFO CTS-0101]  Average sink wire length 9313.40 um
 [INFO CTS-0102]  Path depth 16 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 0
 [INFO CTS-0098] Clock net "clk_regs"
 [INFO CTS-0099]  Sinks 2254
 [INFO CTS-0100]  Leaf buffers 227
 [INFO CTS-0101]  Average sink wire length 4121.94 um
 [INFO CTS-0102]  Path depth 17 - 17
-[INFO CTS-0207]  Leaf load cells 4
+[INFO CTS-0207]  Dummy loads inserted 4
 [INFO RSZ-0047] Found 38 long wires.
 [INFO RSZ-0048] Inserted 160 buffers in 38 nets.
 [INFO CTS-0033] Balancing latency for clock clk