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Merge pull request #281 from The-OpenROAD-Project/check_placement
check_placement macros over fragmented rows are not errors
2 parents c1b6dfb + aaf5e47 commit a15d50f

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8 files changed

+129
-31
lines changed

8 files changed

+129
-31
lines changed

‎src/opendp/src/CheckPlacement.cpp‎

Lines changed: 9 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,9 @@
11
/////////////////////////////////////////////////////////////////////////////
2-
// Original authors: SangGi Do([email protected]), Mingyu
3-
// Woo([email protected])
4-
// (respective Ph.D. advisors: Seokhyeong Kang, Andrew B. Kahng)
5-
// Rewrite by James Cherry, Parallax Software, Inc.
6-
2+
// James Cherry, Parallax Software, Inc.
3+
//
74
// BSD 3-Clause License
85
//
9-
// Copyright (c) 2019, James Cherry, Parallax Software, Inc.
6+
// Copyright (c) 2020, James Cherry, Parallax Software, Inc.
107
// All rights reserved.
118
//
129
// Redistribution and use in source and binary forms, with or without
@@ -68,24 +65,21 @@ Opendp::checkPlacement(bool verbose)
6865
for (Cell &cell : cells_) {
6966
if (isStdCell(&cell)) {
7067
// Site check
71-
if (cell.x_ % site_width_ != 0 || cell.y_ % row_height_ != 0) {
68+
if (cell.x_ % site_width_ != 0 || cell.y_ % row_height_ != 0)
7269
site_failures.push_back(&cell);
73-
}
7470
if (checkPowerLine(cell)) {
7571
checkPowerLine(cell);
7672
power_line_failures.push_back(&cell);
7773
}
74+
if (!checkInRows(cell, grid))
75+
in_rows_failures.push_back(&cell);
7876
}
7977
// Placed check
80-
if (!isPlaced(&cell)) {
78+
if (!isPlaced(&cell))
8179
placed_failures.push_back(&cell);
82-
}
83-
if (!checkInRows(cell, grid)) {
84-
in_rows_failures.push_back(&cell);
85-
}
86-
if (checkOverlap(cell, grid) != nullptr) {
80+
// Overlap check
81+
if (checkOverlap(cell, grid) != nullptr)
8782
overlap_failures.push_back(&cell);
88-
}
8983
}
9084

9185
reportFailures(placed_failures, "Placed", verbose);

‎src/opendp/test/check7.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# std cell abutting block set_placement_padding -right
1+
# check_placement std cell abutting block set_placement_padding -right
22
read_lef Nangate45/Nangate45.lef
33
read_lef extra.lef
44
read_def check6.def

‎src/opendp/test/check8.ok‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Notice 0: Reading LEF file: Nangate45/Nangate45.lef
2+
Notice 0: Created 22 technology layers
3+
Notice 0: Created 27 technology vias
4+
Notice 0: Created 134 library cells
5+
Notice 0: Finished LEF file: Nangate45/Nangate45.lef
6+
Notice 0: Reading LEF file: extra.lef
7+
Notice 0: Created 4 library cells
8+
Notice 0: Finished LEF file: extra.lef
9+
Notice 0:
10+
Reading DEF file: check8.def
11+
Notice 0: Design: single_cell
12+
Notice 0: Created 6 components and 12 component-terminals.
13+
Notice 0: Created 2 special nets and 12 connections.
14+
Notice 0: Finished DEF file: check8.def

‎src/opendp/test/check9.def‎

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,82 @@
1+
VERSION 5.8 ;
2+
NAMESCASESENSITIVE ON ;
3+
DIVIDERCHAR "/" ;
4+
BUSBITCHARS "[]" ;
5+
DESIGN single_cell ;
6+
UNITS DISTANCE MICRONS 2000 ;
7+
DIEAREA ( 0 0 ) ( 20000 20000 ) ;
8+
ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 3800 2800 FS DO 32 BY 1 STEP 380 0 ;
9+
ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 3800 5600 N DO 32 BY 1 STEP 380 0 ;
10+
ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 3800 14000 FS DO 32 BY 1 STEP 380 0 ;
11+
ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 3800 16800 N DO 32 BY 1 STEP 380 0 ;
12+
TRACKS X 190 DO 52 STEP 380 LAYER metal1 ;
13+
TRACKS Y 140 DO 70 STEP 280 LAYER metal1 ;
14+
TRACKS X 190 DO 52 STEP 380 LAYER metal2 ;
15+
TRACKS Y 140 DO 70 STEP 280 LAYER metal2 ;
16+
TRACKS X 190 DO 52 STEP 380 LAYER metal3 ;
17+
TRACKS Y 140 DO 70 STEP 280 LAYER metal3 ;
18+
TRACKS X 190 DO 35 STEP 560 LAYER metal4 ;
19+
TRACKS Y 140 DO 35 STEP 560 LAYER metal4 ;
20+
TRACKS X 190 DO 35 STEP 560 LAYER metal5 ;
21+
TRACKS Y 140 DO 35 STEP 560 LAYER metal5 ;
22+
TRACKS X 190 DO 35 STEP 560 LAYER metal6 ;
23+
TRACKS Y 140 DO 35 STEP 560 LAYER metal6 ;
24+
TRACKS X 190 DO 12 STEP 1600 LAYER metal7 ;
25+
TRACKS Y 140 DO 12 STEP 1600 LAYER metal7 ;
26+
TRACKS X 190 DO 12 STEP 1600 LAYER metal8 ;
27+
TRACKS Y 140 DO 12 STEP 1600 LAYER metal8 ;
28+
TRACKS X 190 DO 6 STEP 3200 LAYER metal9 ;
29+
TRACKS Y 140 DO 6 STEP 3200 LAYER metal9 ;
30+
TRACKS X 190 DO 6 STEP 3200 LAYER metal10 ;
31+
TRACKS Y 140 DO 6 STEP 3200 LAYER metal10 ;
32+
VIAS 3 ;
33+
- via4_960x2800 + VIARULE Via4Array-0 + CUTSIZE 280 280 + LAYERS metal4 metal5 via4 + CUTSPACING 320 320 + ENCLOSURE 40 60 40 60 + ROWCOL 5 2 ;
34+
- via5_960x2800 + VIARULE Via5Array-0 + CUTSIZE 280 280 + LAYERS metal5 metal6 via5 + CUTSPACING 320 320 + ENCLOSURE 40 60 40 60 + ROWCOL 5 2 ;
35+
- via6_960x2800 + VIARULE Via6Array-0 + CUTSIZE 280 280 + LAYERS metal6 metal7 via6 + CUTSPACING 320 320 + ENCLOSURE 340 360 340 360 + ROWCOL 4 1 ;
36+
END VIAS
37+
COMPONENTS 1 ;
38+
- block1 BLOCK1 + FIXED ( 4000 9000 ) N ;
39+
END COMPONENTS
40+
PINS 2 ;
41+
- input + NET input + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 -140 ) N + LAYER metal6 ( -140 -140 ) ( 140 140 ) ;
42+
- out + NET out + DIRECTION OUTPUT + USE SIGNAL + FIXED ( 0 60 ) N + LAYER metal6 ( -140 -140 ) ( 140 140 ) ;
43+
END PINS
44+
SPECIALNETS 2 ;
45+
- VDD ( * VDD ) + USE POWER
46+
+ ROUTED metal6 0 + SHAPE STRIPE ( 136140 106400 ) via6_960x2800
47+
NEW metal5 0 + SHAPE STRIPE ( 136140 106400 ) via5_960x2800
48+
NEW metal4 0 + SHAPE STRIPE ( 136140 106400 ) via4_960x2800
49+
NEW metal6 0 + SHAPE STRIPE ( 24140 106400 ) via6_960x2800
50+
NEW metal5 0 + SHAPE STRIPE ( 24140 106400 ) via5_960x2800
51+
NEW metal4 0 + SHAPE STRIPE ( 24140 106400 ) via4_960x2800
52+
NEW metal6 0 + SHAPE STRIPE ( 136140 26400 ) via6_960x2800
53+
NEW metal5 0 + SHAPE STRIPE ( 136140 26400 ) via5_960x2800
54+
NEW metal4 0 + SHAPE STRIPE ( 136140 26400 ) via4_960x2800
55+
NEW metal6 0 + SHAPE STRIPE ( 24140 26400 ) via6_960x2800
56+
NEW metal5 0 + SHAPE STRIPE ( 24140 26400 ) via5_960x2800
57+
NEW metal4 0 + SHAPE STRIPE ( 24140 26400 ) via4_960x2800
58+
NEW metal7 2800 + SHAPE STRIPE ( 20140 106400 ) ( 180120 106400 )
59+
NEW metal7 2800 + SHAPE STRIPE ( 20140 26400 ) ( 180120 26400 )
60+
NEW metal4 960 + SHAPE STRIPE ( 136140 22400 ) ( 136140 179200 )
61+
NEW metal4 960 + SHAPE STRIPE ( 24140 22400 ) ( 24140 179200 )
62+
NEW metal1 340 + SHAPE FOLLOWPIN ( 3800 14000 ) ( 15960 14000 )
63+
NEW metal1 340 + SHAPE FOLLOWPIN ( 3800 8400 ) ( 15960 8400 )
64+
NEW metal1 340 + SHAPE FOLLOWPIN ( 3800 2800 ) ( 15960 2800 ) ;
65+
- VSS ( * VSS ) + USE GROUND
66+
+ ROUTED metal6 0 + SHAPE STRIPE ( 80140 146400 ) via6_960x2800
67+
NEW metal5 0 + SHAPE STRIPE ( 80140 146400 ) via5_960x2800
68+
NEW metal4 0 + SHAPE STRIPE ( 80140 146400 ) via4_960x2800
69+
NEW metal6 0 + SHAPE STRIPE ( 80140 66400 ) via6_960x2800
70+
NEW metal5 0 + SHAPE STRIPE ( 80140 66400 ) via5_960x2800
71+
NEW metal4 0 + SHAPE STRIPE ( 80140 66400 ) via4_960x2800
72+
NEW metal7 2800 + SHAPE STRIPE ( 20140 146400 ) ( 180120 146400 )
73+
NEW metal7 2800 + SHAPE STRIPE ( 20140 66400 ) ( 180120 66400 )
74+
NEW metal4 960 + SHAPE STRIPE ( 80140 22400 ) ( 80140 179200 )
75+
NEW metal1 340 + SHAPE FOLLOWPIN ( 3800 11200 ) ( 15960 11200 )
76+
NEW metal1 340 + SHAPE FOLLOWPIN ( 3800 5600 ) ( 15960 5600 ) ;
77+
END SPECIALNETS
78+
NETS 2 ;
79+
- input ( PIN input ) + USE SIGNAL ;
80+
- out ( PIN out ) + USE SIGNAL ;
81+
END NETS
82+
END DESIGN

‎src/opendp/test/check9.ok‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
Notice 0: Reading LEF file: Nangate45/Nangate45.lef
2+
Notice 0: Created 22 technology layers
3+
Notice 0: Created 27 technology vias
4+
Notice 0: Created 134 library cells
5+
Notice 0: Finished LEF file: Nangate45/Nangate45.lef
6+
Notice 0: Reading LEF file: extra.lef
7+
Notice 0: Created 4 library cells
8+
Notice 0: Finished LEF file: extra.lef
9+
Notice 0:
10+
Reading DEF file: check9.def
11+
Notice 0: Design: single_cell
12+
Notice 0: Created 2 pins.
13+
Notice 0: Created 1 components and 7 component-terminals.
14+
Notice 0: Created 2 special nets and 2 connections.
15+
Notice 0: Created 2 nets and 0 connections.
16+
Notice 0: Finished DEF file: check9.def

‎src/opendp/test/check9.tcl‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# check_placement block off grid (no error)
2+
read_lef Nangate45/Nangate45.lef
3+
read_lef extra.lef
4+
read_def check9.def
5+
check_placement -verbose

‎src/opendp/test/extra.lef‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -36,49 +36,34 @@ MACRO BLOCK1
3636
SYMMETRY Y ;
3737
PIN A
3838
DIRECTION INPUT ;
39-
ANTENNAPARTIALMETALAREA 0.02275 LAYER metal1 ;
40-
ANTENNAPARTIALMETALSIDEAREA 0.0793 LAYER metal1 ;
41-
ANTENNAGATEAREA 0.05225 ;
4239
PORT
4340
LAYER metal1 ;
4441
POLYGON 0.63 0.525 0.76 0.525 0.76 0.7 0.63 0.7 ;
4542
END
4643
END A
4744
PIN B
4845
DIRECTION INPUT ;
49-
ANTENNAPARTIALMETALAREA 0.021875 LAYER metal1 ;
50-
ANTENNAPARTIALMETALSIDEAREA 0.078 LAYER metal1 ;
51-
ANTENNAGATEAREA 0.05225 ;
5246
PORT
5347
LAYER metal1 ;
5448
POLYGON 0.44 0.525 0.565 0.525 0.565 0.7 0.44 0.7 ;
5549
END
5650
END B
5751
PIN C1
5852
DIRECTION INPUT ;
59-
ANTENNAPARTIALMETALAREA 0.021875 LAYER metal1 ;
60-
ANTENNAPARTIALMETALSIDEAREA 0.078 LAYER metal1 ;
61-
ANTENNAGATEAREA 0.05225 ;
6253
PORT
6354
LAYER metal1 ;
6455
POLYGON 0.06 0.525 0.185 0.525 0.185 0.7 0.06 0.7 ;
6556
END
6657
END C1
6758
PIN C2
6859
DIRECTION INPUT ;
69-
ANTENNAPARTIALMETALAREA 0.021875 LAYER metal1 ;
70-
ANTENNAPARTIALMETALSIDEAREA 0.078 LAYER metal1 ;
71-
ANTENNAGATEAREA 0.05225 ;
7260
PORT
7361
LAYER metal1 ;
7462
POLYGON 0.25 0.525 0.375 0.525 0.375 0.7 0.25 0.7 ;
7563
END
7664
END C2
7765
PIN ZN
7866
DIRECTION OUTPUT ;
79-
ANTENNAPARTIALMETALAREA 0.1862 LAYER metal1 ;
80-
ANTENNAPARTIALMETALSIDEAREA 0.6123 LAYER metal1 ;
81-
ANTENNADIFFAREA 0.2926 ;
8267
PORT
8368
LAYER metal1 ;
8469
POLYGON 1.375 0.15 1.445 0.15 1.445 0.56 1.75 0.56 1.75 0.15 1.82 0.15 1.82 1.175 1.75 1.175 1.75 0.7 1.445 0.7 1.445 1.175 1.375 1.175 ;

‎src/opendp/test/regression_tests.tcl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@ record_tests {
66
check5
77
check6
88
check7
9+
check8
10+
check9
911
fence01
1012
fence02
1113
fence03

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