rsz: Fix ideal clock handling in driver delay modeling

In buffering, when modeling the driver delay change due to a changed
load, if the driver arc goes from a clock pin to a register output pin,
make the change to consider an idealized clock arrival on the clock pin
instead of looking up the arrival value on the vertex.

For arcs going from an ideal clock pin we already override the slew
(via the helper `graph_delay_calc_->edgeFromSlew()`), but an arrival
override was missing until now.

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

src/rsz/src/Rebuffer.cc

@@ -21,6 +21,7 @@ namespace rsz {
 
 using odb::dbSigType;
 using sta::ArcDcalcResult;
+using sta::Arrival;
 using sta::Edge;
 using sta::fuzzyGreater;
 using sta::fuzzyGreaterEqual;
@@ -241,8 +242,12 @@ std::tuple<Delay, Delay, Slew> Rebuffer::drvrPinTiming(const BnetPtr& bnet)
                                        load_pin_index_map,
                                        dcalc_ap);
       rf_delay = dcalc_result.gateDelay();
-      rf_correction = arrival_path->arrival()
-                      - (driver_path->arrival() + dcalc_result.gateDelay());
+
+      Arrival prev_arrival = driver_path->isClock(sta_)
+                                 ? search_->clkPathArrival(driver_path)
+                                 : driver_path->arrival();
+      rf_correction
+          = arrival_path->arrival() - (prev_arrival + dcalc_result.gateDelay());
       rf_slew = dcalc_result.drvrSlew();
     } else {
       rf_delay = 0;