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Added more test cases to check bus wires b/w hard macro instances.
Signed-off-by: Jaehyun Kim <[email protected]>
1 parent 5951c01 commit faf08d6

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9 files changed

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+559
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lines changed

‎src/rsz/test/BUILD‎

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@@ -10,6 +10,8 @@ TESTS = [
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"buffer_ports10",
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"buffer_ports11",
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"buffer_ports11_hier",
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"buffer_ports12",
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"buffer_ports12_hier",
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"buffer_ports3",
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"buffer_ports4",
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"buffer_ports5",

‎src/rsz/test/CMakeLists.txt‎

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@@ -16,6 +16,8 @@ or_integration_tests(
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buffer_ports10
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buffer_ports11
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buffer_ports11_hier
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buffer_ports12
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buffer_ports12_hier
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buffer_varying_lengths
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clone_flat
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clone_hier

‎src/rsz/test/buffer_ports12.ok‎

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[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
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[INFO ODB-0227] LEF file: Nangate45/fakeram45_64x7.lef, created 1 library cells
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clk
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count: 1
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sram0_ce_in
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count: 1
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sram0_we_in
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count: 1
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{sram0_addr_in[0]} {sram0_addr_in[1]} {sram0_addr_in[2]} {sram0_addr_in[3]} {sram0_addr_in[4]} {sram0_addr_in[5]}
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count: 6
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{sram0_w_mask_in[0]} {sram0_w_mask_in[1]} {sram0_w_mask_in[2]} {sram0_w_mask_in[3]} {sram0_w_mask_in[4]} {sram0_w_mask_in[5]} {sram0_w_mask_in[6]}
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count: 7
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sram1_ce_in
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count: 1
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sram1_we_in
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count: 1
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{sram1_addr_in[0]} {sram1_addr_in[1]} {sram1_addr_in[2]} {sram1_addr_in[3]} {sram1_addr_in[4]} {sram1_addr_in[5]}
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count: 6
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{sram1_w_mask_in[0]} {sram1_w_mask_in[1]} {sram1_w_mask_in[2]} {sram1_w_mask_in[3]} {sram1_w_mask_in[4]} {sram1_w_mask_in[5]} {sram1_w_mask_in[6]}
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count: 7
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clk
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count: 1
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{addr_in[0]} {addr_in[1]} {addr_in[2]} {addr_in[3]} {addr_in[4]} {addr_in[5]}
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count: 6
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clk
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count: 1
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{addr_in[0]} {addr_in[1]} {addr_in[2]} {addr_in[3]} {addr_in[4]} {addr_in[5]}
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count: 6
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[INFO RSZ-0027] Inserted 31 BUF_X1 input buffers.
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[INFO RSZ-0028] Inserted 0 BUF_X1 output buffers.
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No differences found.

‎src/rsz/test/buffer_ports12.tcl‎

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# Check bus ports of hard macro instances in flat flow
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source "helpers.tcl"
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proc print_info { objs } {
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set obj_names {}
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foreach obj $objs {
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lappend obj_names [get_name $obj]
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}
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puts "[lsort $obj_names]"
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puts "count: [llength $objs]"
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puts ""
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}
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read_liberty Nangate45/Nangate45_typ.lib
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read_liberty Nangate45/fakeram45_64x7.lib
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read_lef Nangate45/Nangate45.lef
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read_lef Nangate45/fakeram45_64x7.lef
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read_verilog buffer_ports12.v
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link_design top
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print_info [get_ports clk]
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print_info [get_ports sram0_ce_in]
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print_info [get_ports sram0_we_in]
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print_info [get_ports sram0_addr_in*]
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print_info [get_ports sram0_w_mask_in*]
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print_info [get_ports sram1_ce_in]
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print_info [get_ports sram1_we_in]
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print_info [get_ports sram1_addr_in*]
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print_info [get_ports sram1_w_mask_in*]
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print_info [get_pins sram0/clk]
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print_info [get_pins sram0/addr_in*]
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print_info [get_pins sram1/clk]
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print_info [get_pins sram1/addr_in*]
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buffer_ports
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set verilog_file [make_result_file buffer_ports12.v]
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write_verilog $verilog_file
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diff_files buffer_ports12.vok $verilog_file

‎src/rsz/test/buffer_ports12.v‎

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module top (
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input clk,
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input sram0_ce_in,
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input sram0_we_in,
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input [5:0] sram0_addr_in,
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input [6:0] sram0_w_mask_in,
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input sram1_ce_in,
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input sram1_we_in,
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input [5:0] sram1_addr_in,
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input [6:0] sram1_w_mask_in
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);
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wire [6:0] sram0_rd_out;
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wire [6:0] sram1_rd_out;
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fakeram45_64x7 sram0 (
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.clk(clk),
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.ce_in(sram0_ce_in),
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.we_in(sram0_we_in),
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.addr_in(sram0_addr_in),
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.wd_in(sram1_rd_out),
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.w_mask_in(sram0_w_mask_in),
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.rd_out(sram0_rd_out)
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);
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fakeram45_64x7 sram1 (
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.clk(clk),
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.ce_in(sram1_ce_in),
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.we_in(sram1_we_in),
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.addr_in(sram1_addr_in),
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.wd_in(sram0_rd_out),
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.w_mask_in(sram1_w_mask_in),
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.rd_out(sram1_rd_out)
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);
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endmodule

‎src/rsz/test/buffer_ports12.vok‎

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module top (clk,
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sram0_ce_in,
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sram0_we_in,
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sram1_ce_in,
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sram1_we_in,
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sram0_addr_in,
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sram0_w_mask_in,
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sram1_addr_in,
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sram1_w_mask_in);
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input clk;
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input sram0_ce_in;
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input sram0_we_in;
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input sram1_ce_in;
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input sram1_we_in;
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input [5:0] sram0_addr_in;
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input [6:0] sram0_w_mask_in;
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input [5:0] sram1_addr_in;
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input [6:0] sram1_w_mask_in;
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wire net1;
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wire net2;
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wire net3;
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wire net4;
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wire net5;
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wire net6;
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wire net7;
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wire net8;
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wire net9;
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wire net10;
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wire net11;
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wire net12;
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wire net13;
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wire net14;
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wire net15;
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wire net16;
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wire net17;
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wire net18;
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wire net19;
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wire net20;
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wire net21;
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wire net22;
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wire net23;
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wire net24;
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wire net25;
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wire net26;
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wire net27;
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wire net28;
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wire net29;
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wire net30;
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wire net31;
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wire [6:0] sram0_rd_out;
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wire [6:0] sram1_rd_out;
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fakeram45_64x7 sram0 (.we_in(net16),
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.ce_in(net8),
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.clk(net1),
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.addr_in({net7,
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net6,
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net5,
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net4,
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net3,
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net2}),
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.rd_out({sram0_rd_out[6],
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sram0_rd_out[5],
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sram0_rd_out[4],
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sram0_rd_out[3],
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sram0_rd_out[2],
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sram0_rd_out[1],
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sram0_rd_out[0]}),
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.w_mask_in({net15,
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net14,
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net13,
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net12,
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net11,
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net10,
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net9}),
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.wd_in({sram1_rd_out[6],
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sram1_rd_out[5],
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sram1_rd_out[4],
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sram1_rd_out[3],
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sram1_rd_out[2],
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sram1_rd_out[1],
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sram1_rd_out[0]}));
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fakeram45_64x7 sram1 (.we_in(net31),
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.ce_in(net23),
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.clk(net1),
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.addr_in({net22,
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net21,
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net20,
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net19,
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net18,
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net17}),
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.rd_out({sram1_rd_out[6],
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sram1_rd_out[5],
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sram1_rd_out[4],
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sram1_rd_out[3],
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sram1_rd_out[2],
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sram1_rd_out[1],
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sram1_rd_out[0]}),
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.w_mask_in({net30,
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net29,
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net28,
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net27,
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net26,
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net25,
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net24}),
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.wd_in({sram0_rd_out[6],
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sram0_rd_out[5],
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sram0_rd_out[4],
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sram0_rd_out[3],
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sram0_rd_out[2],
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sram0_rd_out[1],
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sram0_rd_out[0]}));
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BUF_X1 input1 (.A(clk),
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.Z(net1));
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BUF_X1 input2 (.A(sram0_addr_in[0]),
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.Z(net2));
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BUF_X1 input3 (.A(sram0_addr_in[1]),
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.Z(net3));
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BUF_X1 input4 (.A(sram0_addr_in[2]),
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.Z(net4));
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BUF_X1 input5 (.A(sram0_addr_in[3]),
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.Z(net5));
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BUF_X1 input6 (.A(sram0_addr_in[4]),
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.Z(net6));
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BUF_X1 input7 (.A(sram0_addr_in[5]),
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.Z(net7));
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BUF_X1 input8 (.A(sram0_ce_in),
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.Z(net8));
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BUF_X1 input9 (.A(sram0_w_mask_in[0]),
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.Z(net9));
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BUF_X1 input10 (.A(sram0_w_mask_in[1]),
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.Z(net10));
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BUF_X1 input11 (.A(sram0_w_mask_in[2]),
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.Z(net11));
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BUF_X1 input12 (.A(sram0_w_mask_in[3]),
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.Z(net12));
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BUF_X1 input13 (.A(sram0_w_mask_in[4]),
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.Z(net13));
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BUF_X1 input14 (.A(sram0_w_mask_in[5]),
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.Z(net14));
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BUF_X1 input15 (.A(sram0_w_mask_in[6]),
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.Z(net15));
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BUF_X1 input16 (.A(sram0_we_in),
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.Z(net16));
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BUF_X1 input17 (.A(sram1_addr_in[0]),
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.Z(net17));
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BUF_X1 input18 (.A(sram1_addr_in[1]),
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.Z(net18));
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BUF_X1 input19 (.A(sram1_addr_in[2]),
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.Z(net19));
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BUF_X1 input20 (.A(sram1_addr_in[3]),
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.Z(net20));
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BUF_X1 input21 (.A(sram1_addr_in[4]),
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.Z(net21));
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BUF_X1 input22 (.A(sram1_addr_in[5]),
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.Z(net22));
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BUF_X1 input23 (.A(sram1_ce_in),
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.Z(net23));
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BUF_X1 input24 (.A(sram1_w_mask_in[0]),
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.Z(net24));
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BUF_X1 input25 (.A(sram1_w_mask_in[1]),
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.Z(net25));
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BUF_X1 input26 (.A(sram1_w_mask_in[2]),
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.Z(net26));
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BUF_X1 input27 (.A(sram1_w_mask_in[3]),
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.Z(net27));
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BUF_X1 input28 (.A(sram1_w_mask_in[4]),
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.Z(net28));
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BUF_X1 input29 (.A(sram1_w_mask_in[5]),
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.Z(net29));
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BUF_X1 input30 (.A(sram1_w_mask_in[6]),
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.Z(net30));
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BUF_X1 input31 (.A(sram1_we_in),
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.Z(net31));
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endmodule

‎src/rsz/test/buffer_ports12_hier.ok‎

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[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
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[INFO ODB-0227] LEF file: Nangate45/fakeram45_64x7.lef, created 1 library cells
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[WARNING ORD-0011] Hierarchical flow (-hier) is currently in development and may cause multiple issues. Do not use in production environments.
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clk
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count: 1
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sram0_ce_in
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count: 1
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sram0_we_in
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count: 1
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{sram0_addr_in[0]} {sram0_addr_in[1]} {sram0_addr_in[2]} {sram0_addr_in[3]} {sram0_addr_in[4]} {sram0_addr_in[5]}
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count: 6
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{sram0_w_mask_in[0]} {sram0_w_mask_in[1]} {sram0_w_mask_in[2]} {sram0_w_mask_in[3]} {sram0_w_mask_in[4]} {sram0_w_mask_in[5]} {sram0_w_mask_in[6]}
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count: 7
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sram1_ce_in
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count: 1
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sram1_we_in
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count: 1
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{sram1_addr_in[0]} {sram1_addr_in[1]} {sram1_addr_in[2]} {sram1_addr_in[3]} {sram1_addr_in[4]} {sram1_addr_in[5]}
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count: 6
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{sram1_w_mask_in[0]} {sram1_w_mask_in[1]} {sram1_w_mask_in[2]} {sram1_w_mask_in[3]} {sram1_w_mask_in[4]} {sram1_w_mask_in[5]} {sram1_w_mask_in[6]}
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count: 7
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clk
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count: 1
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{addr_in[0]} {addr_in[1]} {addr_in[2]} {addr_in[3]} {addr_in[4]} {addr_in[5]}
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count: 6
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clk
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count: 1
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{addr_in[0]} {addr_in[1]} {addr_in[2]} {addr_in[3]} {addr_in[4]} {addr_in[5]}
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count: 6
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[INFO RSZ-0027] Inserted 31 BUF_X1 input buffers.
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[INFO RSZ-0028] Inserted 0 BUF_X1 output buffers.
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No differences found.

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