mpl2: IOs abstraction adaptation to ORFS flow - first version (simplified)

[AcKoucher]

Resolve the first top level task in #5669.
Resolve #6050.
Resolve #4867.

Introductory Considerations

• This is the first step of the enhancements to adapt the IOs abstractions inside mpl2 to ORFS flow.
• This first version will not consider the dimensions of the constraints whether they are -exclude constraints or pins' constraint regions.

Goals

1. Improve QoR in terms of WL.
2. Ease the life of the annealer for some cases (e.g., sky130hd/uW) that require extreme virtual std cell utilization configurations to converge.
3. Further steps into switching from manual mpl to mpl2 for cases such as sky130hd/chameleon (This will still require clustering work)

Main Changes

Modify IO Clusters

IO clusters that represent bundledIOs created from the pins placed by random PPL are now groups of unplaced IOs with the same constraints based on the following:

• Individual Pin Constraints:

  • If an IO has a constraint region in a certain boundary, it is constrained to that entire boundary.
  • If an IO has no constraint region, it is constrained to all boundaries.

• Global Pins' Constraints (-exclude)

  • If a boundary has more than 70% of its extension blocked, it is considered a blocked boundary for IOs.

What Annealing Sees

• WL between a cluster/macro (soft/hard) M and an IO cluster IO is represented as follow:
  • If IO represents pins constrained to a certain boundary A, WL is the minimum distance between M's bundled center pin and A.
  • If IO represents unconstrained pins, WL is the minimum distance between M's bundled center pin and the closest non-blocked boundary.

Obs: This distance only reduces cost when M is inside the outline.

Collateral Changes

Needed for the Approach to Work

1. Add Cluster support to HardMacro so that SA can check if they are IO clusters' fixed terminals.
2. Make both Soft/HardMacroSACores have access to the PhisycalHierarchical data where the global constraints are now stored.
3. Make fixed terminals that represent IO clusters have the cluster data inside them so that this data is accessible inside SA for both Soft and Hard. I.e., the cluster of a fixed terminal that represents an IO cluster will be != nullptr

Blockages for Pin Access

Generated based on a combination of both global and individual pins' constraints:

1. If there are pins constrained to a certain boundary, we'll generate a blockage for that boundary.
2. If there are no pins constrained a boundary A but there are pins constrained to all boundaries, A won't have a pin access blockage. (Specially important so that SA has more freedom).
3. The depth of the blockage is a combination of the extension of IO clusters and std cell area (this can definitely be further improved to consider the IOs density)

Orientation Improvement

When iterating a net, compute HPWL based on:

1. If a pin has a constraint region, use its center.
2. If a pin doesn't have a constraint region, use the closest point of the closest boundary to that macro pin.

Debug Mode

1. Blocked boundaries are marked with a red X in the center of their extension
2. Draw distance to constraint || closest boundary only when the cluster/macro is inside the outline

[maliberty]

There a couple designs that need metrics update.

Is there a PR for this?

[AcKoucher]

Is there a PR for this?

I opened #2582. However, a metrics conflict emerged from another PR. I'm re-running Secure-CI to update the metrics correctly.

[maliberty]

@AcKoucher what remains to merge this?

[AcKoucher]

@maliberty This PR is blocked by a gpl divergence in uW (See #6235).

[AcKoucher]

I resolved the conflicts here.

With the updates from master, GPL no longer diverges in uW. However, now GRT is throwing an error due to high congestion in post-drt. I'm investigating.

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[AcKoucher]

Updating..

I ran a new Secure-CI with a custom GRT routing layer adjustment and it solved uW's congestion problem.
However, now g12/ca53 is failing in DPL.

Edit:
The failure happens at CTS legalization. It looks like the clock gaters enhancement in #6134 added a very large number of buffers and put the design in the limit of having a legalization problem - the changes here unluckily triggered it. @arthurjolo is investigating.

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[AcKoucher]

Settings changes and metrics update in #2706

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"