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Co-authored-by: Krzysztof Bieganski <kbieganski@antmicro.com> Signed-off-by: Jan Bylicki <jbylicki@antmicro.com> Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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I'll hold off on review until you resolve the various failures |
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Note that you will need to make this work with Bazel as well as cmake |
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Sure, no problem. Shouldn't the CI run on our fork as well? (only the security check does) |
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I don't think we allow Jenkins to be used on forks as that would allow arbitrary workloads to be started (eg someone will inevitably replace OR with a bit coin miner). |
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Right, but I mean the format checks etc, that's just GitHub Actions, right? |
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I expect those would run in a fork |
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@vvbandeira @maliberty Can you take a look at the scan code ci step, looks like they need a whitelist? |
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I don't think we should worry about the whitelist until we settle the question of module names. |
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What name would you propose for the logic extractor? It extracts/exports logic to ABC. How about just |
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I don't think of it as extracting logic but more of a local cutout or window. Extraction is a very overloaded word as well and often refers to computing a derived result (e.g. rc extraction, connectivity extraction, device parameter extraction, etc). I expect the idea of a small piece of logic to be useful in many context so abc would not be a good name. I think rsz will want the same for example. I like 'Logic Cutout' but am open to other ideas. |
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"logic partition"? Also, I am curious about how this compares to the clock gating done at the synthesis level. I think Yosys supports this now, and it is generally more suitable to be done at the synthesis stage. While 15% power savings are nothing to scoff at, I usually see 30-60% savings from commercial tools. |
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Partition sounds a bit like min-cut paritioning of par/TritonPart. |
This is a similar technique as what's used in other tools. The one in Yosys just goes off trivial enable signals which doesn't actually save much power since those signals have very low toggle rates in practice. I asked Yosys to implement the former, and it didn't really deliver the results I was expecting. |
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@maliberty I think your name suggestions need to be a 3 letter monicor not a general thing about Logic Extraction. The class is already called LogicCut. I would propose syn, and it would encapsulate synthesis related functionality. Or throw it in utl, or get rid of the 3 letter name requirement. |
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@kbieganski The decision has been made by Matt and I. Please rename it |
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It feels like too much of rmp got pulled into lext. I stopped commenting on it per file but I feel lext should not need an abc dependency and should be generic infrastructure. Rmp is the right place for applying abc to a logic cut. |
Logic cuts build mapped abc networks. So it will by default need an abc dep. That's part of the design of logic cut. It can be built from STA and emit networks in other formats, and take those other formats and insert them back into odb/sta |
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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clang-tidy review says "All clean, LGTM! 👍" |
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clang-tidy review says "All clean, LGTM! 👍" |
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Please resolve the merge conflicts |
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I'm in the process of doing that. Latest changes are a bit tricky to integrate. |
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
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clang-tidy review says "All clean, LGTM! 👍" |
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Please ping when this is ready for review |
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@maliberty It's ready, the CI failures seem to be some network issues. |
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cgt.ibex_sky130hd.tcl failed in pr-merge. Please merge master and resolve. |
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The CI is green now. |
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@kbieganski since merging this we find it fails non-deterministically in our ci for the aes_nangate45.tcl test. I'm looking into it but I hope you can help as well as the author. If the cause isn't found soon I will revert or disable this change. |
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I'll help. The diff from the artifacts is: 30,32c30
< Differences found at line 53020.
< .ZN(_02445_));
< .ZN(_0
---
> No differences found. So it's as if the file was cut off, but the one in the artifacts is correct. Are the tests run in parallel? They write to the same file, so perhaps one test overwrites the other's result? |
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@kbieganski yes the tests can run in parallel, you might want to update the tests to write the unique files based on the test name to avoid this |
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You should use make_result_file - see any other unit test for examples |
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I did run with asan while trying to figure it out and there are a bunch of leaks from within abc. I presume they are somehow related to cgt's usage: |
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I'll take a look at those |
6 participants
Adds
cgt, a module that performs automatic clock gating based on this paper.It uses the logic extractor from
rmp, so that part was extracted intolext, a common module for bothrmpandcgt.ABC is used for verifying gating conditions.
Example power results
Ibex simple system on Sky130
Before
After
A proprietary design on ASAP7
Before
After