DPL: Remove the use of unordered_set in searchNearestSite

src/cts/test/array.ok

@@ -125,11 +125,11 @@ Dummys used:
 [INFO RSZ-0048] Inserted 112 buffers in 38 nets.
 Placement Analysis
 ---------------------------------
-total displacement       4567.0 u
+total displacement       4569.6 u
 average displacement        1.4 u
 max displacement          146.7 u
 original HPWL          189367.9 u
-legalized HPWL         190335.5 u
+legalized HPWL         190345.7 u
 delta HPWL                    1 %
 
 Clock clk
@@ -177,9 +177,9 @@ Path Type: max
    0.04    1.11 ^ wire10/Z (BUF_X8)
    0.05    1.16 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
    0.00    1.16 ^ inst_1_1/clk (array_tile)
-   0.21    1.38 ^ inst_1_1/e_out (array_tile)
-   0.00    1.38 ^ inst_2_1/w_in (array_tile)
-           1.38   data arrival time
+   0.21    1.37 ^ inst_1_1/e_out (array_tile)
+   0.00    1.37 ^ inst_2_1/w_in (array_tile)
+           1.37   data arrival time
 
    5.00    5.00   clock clk (rise edge)
    0.00    5.00   clock source latency
@@ -216,7 +216,7 @@ Path Type: max
            6.07   data required time
 ---------------------------------------------------------
            6.07   data required time
-          -1.38   data arrival time
+          -1.37   data arrival time
 ---------------------------------------------------------
            4.69   slack (MET)
 

src/cts/test/array_ins_delay.ok

@@ -115,11 +115,11 @@
 [INFO RSZ-0048] Inserted 112 buffers in 38 nets.
 Placement Analysis
 ---------------------------------
-total displacement       4576.2 u
+total displacement       4577.7 u
 average displacement        1.4 u
 max displacement          146.7 u
 original HPWL          189368.6 u
-legalized HPWL         190344.8 u
+legalized HPWL         190349.6 u
 delta HPWL                    1 %
 
 Clock clk
@@ -167,9 +167,9 @@ Path Type: max
    0.04    1.11 ^ wire10/Z (BUF_X8)
    0.05    1.16 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
    0.00    1.16 ^ inst_1_1/clk (array_tile)
-   0.21    1.38 ^ inst_1_1/e_out (array_tile)
-   0.00    1.38 ^ inst_2_1/w_in (array_tile)
-           1.38   data arrival time
+   0.21    1.37 ^ inst_1_1/e_out (array_tile)
+   0.00    1.37 ^ inst_2_1/w_in (array_tile)
+           1.37   data arrival time
 
    5.00    5.00   clock clk (rise edge)
    0.00    5.00   clock source latency
@@ -206,7 +206,7 @@ Path Type: max
            6.07   data required time
 ---------------------------------------------------------
            6.07   data required time
-          -1.38   data arrival time
+          -1.37   data arrival time
 ---------------------------------------------------------
            4.69   slack (MET)
 

src/cts/test/array_no_blockages.ok

@@ -114,11 +114,11 @@
 [INFO RSZ-0048] Inserted 112 buffers in 38 nets.
 Placement Analysis
 ---------------------------------
-total displacement       4366.2 u
+total displacement       4368.8 u
 average displacement        1.4 u
 max displacement          146.3 u
 original HPWL          190067.1 u
-legalized HPWL         191162.0 u
+legalized HPWL         191160.9 u
 delta HPWL                    1 %
 
 Clock clk

src/cts/test/array_repair_clock_nets.ok

@@ -128,11 +128,11 @@ Dummys used:
 [INFO RSZ-0058] Using max wire length 693um.
 Placement Analysis
 ---------------------------------
-total displacement       4508.1 u
+total displacement       4509.5 u
 average displacement        1.4 u
 max displacement          146.7 u
 original HPWL          189361.4 u
-legalized HPWL         190291.0 u
+legalized HPWL         190300.6 u
 delta HPWL                    0 %
 
 Clock clk

src/cts/test/simple_test_hier.ok

@@ -77,7 +77,7 @@ delta HPWL                    0 %
 [INFO CTS-0098] Clock net "clk"
 [INFO CTS-0099]  Sinks 17
 [INFO CTS-0100]  Leaf buffers 0
-[INFO CTS-0101]  Average sink wire length 17.16 um
+[INFO CTS-0101]  Average sink wire length 17.12 um
 [INFO CTS-0102]  Path depth 2 - 2
 [INFO CTS-0207]  Leaf load cells 1
 No differences found.

src/cts/test/simple_test_hier_out.vok

@@ -5,18 +5,16 @@ module test_16_sinks (clk);
  wire clknet_1_0__leaf_clk;
  wire clknet_0_clk;
 
- INV_X1 clkload0 (.A(clknet_1_1__leaf_clk));
+ INV_X1 clkload0 (.A(clknet_1_0__leaf_clk));
  CLKBUF_X3 clkbuf_1_1__f_clk (.A(clknet_0_clk),
     .Z(clknet_1_1__leaf_clk));
  CLKBUF_X3 clkbuf_1_0__f_clk (.A(clknet_0_clk),
     .Z(clknet_1_0__leaf_clk));
  CLKBUF_X3 clkbuf_0_clk (.A(clk),
     .Z(clknet_0_clk));
- flop_pair U1 (.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
- flop_pair_U2 U2 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
-    .clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
- flop_pair_U3 U3 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
-    .clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
+ flop_pair U1 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk));
+ flop_pair_U2 U2 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk));
+ flop_pair_U3 U3 (.clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
  flop_pair_U4 U4 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
     .clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
  flop_pair_U5 U5 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
@@ -28,29 +26,25 @@ module test_16_sinks (clk);
  flop_pair_U8 U8 (.clknet_1_1__leaf_clk_i(clknet_1_1__leaf_clk),
     .clknet_1_0__leaf_clk_i(clknet_1_0__leaf_clk));
 endmodule
-module flop_pair (clknet_1_0__leaf_clk_i);
- input clknet_1_0__leaf_clk_i;
+module flop_pair (clknet_1_1__leaf_clk_i);
+ input clknet_1_1__leaf_clk_i;
 
 
- DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
- DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
+ DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
+ DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
 endmodule
-module flop_pair_U2 (clknet_1_1__leaf_clk_i,
-    clknet_1_0__leaf_clk_i);
+module flop_pair_U2 (clknet_1_1__leaf_clk_i);
  input clknet_1_1__leaf_clk_i;
- input clknet_1_0__leaf_clk_i;
 
 
  DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
- DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
+ DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
 endmodule
-module flop_pair_U3 (clknet_1_1__leaf_clk_i,
-    clknet_1_0__leaf_clk_i);
- input clknet_1_1__leaf_clk_i;
+module flop_pair_U3 (clknet_1_0__leaf_clk_i);
  input clknet_1_0__leaf_clk_i;
 
 
- DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
+ DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
  DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
 endmodule
 module flop_pair_U4 (clknet_1_1__leaf_clk_i,
@@ -77,8 +71,8 @@ module flop_pair_U6 (clknet_1_1__leaf_clk_i,
  input clknet_1_0__leaf_clk_i;
 
 
- DFF_X1 ff1 (.CK(clknet_1_1__leaf_clk_i));
- DFF_X1 ff2 (.CK(clknet_1_0__leaf_clk_i));
+ DFF_X1 ff1 (.CK(clknet_1_0__leaf_clk_i));
+ DFF_X1 ff2 (.CK(clknet_1_1__leaf_clk_i));
 endmodule
 module flop_pair_U7 (clknet_1_1__leaf_clk_i,
     clknet_1_0__leaf_clk_i);

src/dpl/src/Place.cpp

@@ -744,17 +744,28 @@ PixelPt Opendp::searchNearestSite(const Node* cell,
       return manhattan_distance == other.manhattan_distance;
     }
   };
+
+  // Check the first candidate to avoid unnecessary priority queue creation.
+  GridPt center{x, y};
+  if (canBePlaced(cell, center.x, center.y)) {
+    return PixelPt(grid_->gridPixel(center.x, center.y), center.x, center.y);
+  }
+
   std::priority_queue<PQ_entry, std::vector<PQ_entry>, std::greater<PQ_entry>>
       positionsHeap;
-  std::unordered_set<GridPt> visited;
-  GridPt center{x, y};
-  positionsHeap.push(PQ_entry{0, center});
-  visited.insert(center);
 
-  const vector<GridPt> neighbors = {{GridX(-1), GridY(0)},
-                                    {GridX(1), GridY(0)},
-                                    {GridX(0), GridY(-1)},
-                                    {GridX(0), GridY(1)}};
+  auto addIfInBounds = [&](GridPt const& n) {
+    if (n.x >= x_min && n.x <= x_max && n.y >= y_min && n.y <= y_max) {
+      positionsHeap.push(PQ_entry{calcDist(center, n), n});
+    }
+  };
+
+  // Add the 4 immediate neighbors of the center.
+  addIfInBounds({center.x + 1, center.y});
+  addIfInBounds({center.x - 1, center.y});
+  addIfInBounds({center.x, center.y + 1});
+  addIfInBounds({center.x, center.y - 1});
+
   while (!positionsHeap.empty()) {
     const GridPt nearest = positionsHeap.top().p;
     positionsHeap.pop();
@@ -764,21 +775,26 @@ PixelPt Opendp::searchNearestSite(const Node* cell,
           grid_->gridPixel(nearest.x, nearest.y), nearest.x, nearest.y);
     }
 
-    // Put neighbors in the queue
-    for (GridPt offset : neighbors) {
-      GridPt neighbor = {nearest.x + offset.x, nearest.y + offset.y};
-      // Check if it was already put in the queue
-      if (visited.count(neighbor) > 0) {
-        continue;
+    auto getSign = [](auto const grid_coord, auto center_coord) {
+      if (grid_coord > center_coord) {
+        return 1;
       }
-      // Check limits
-      if (neighbor.x < x_min || neighbor.x > x_max || neighbor.y < y_min
-          || neighbor.y > y_max) {
-        continue;
-      }
-
-      visited.insert(neighbor);
-      positionsHeap.push(PQ_entry{calcDist(center, neighbor), neighbor});
+      return -1;
+    };
+
+    // Expand out in a "circle"
+    if (nearest.x == center.x) {  // on y-axis
+      // top side only expands up and bottom side only expands down
+      int sign = getSign(nearest.y, center.y);
+      addIfInBounds({nearest.x, nearest.y + sign});
+
+      // go left and right
+      addIfInBounds({nearest.x + 1, nearest.y});
+      addIfInBounds({nearest.x - 1, nearest.y});
+    } else {
+      // Left half expands left, right half expands right.
+      int sign = getSign(nearest.x, center.x);
+      addIfInBounds({nearest.x + sign, nearest.y});
     }
   }
   return PixelPt();