Merge branch 'YosysHQ:main' into master

Author: eder-matheus

.github/workflows/extra-builds.yml

@@ -36,7 +36,7 @@ jobs:
 
   vs-build:
     name: Visual Studio build
-    runs-on: windows-2019
+    runs-on: windows-latest
     needs: [vs-prep, pre_job]
     if: needs.pre_job.outputs.should_skip != 'true'
     steps:  

.github/workflows/test-build.yml

@@ -40,6 +40,7 @@ jobs:
     strategy:
       matrix:
         os: [ubuntu-latest, macos-latest]
+        sanitizer: [undefined, address]
       fail-fast: false
     steps:
       - name: Checkout Yosys
@@ -57,7 +58,7 @@ jobs:
           mkdir build
           cd build
           make -f ../Makefile config-$CC
-          echo 'SANITIZER = undefined' >> Makefile.conf
+          echo 'SANITIZER = ${{ matrix.sanitizer }}' >> Makefile.conf
           make -f ../Makefile -j$procs ENABLE_LTO=1
 
       - name: Log yosys-config output
@@ -73,7 +74,7 @@ jobs:
       - name: Store build artifact
         uses: actions/upload-artifact@v4
         with:
-          name: build-${{ matrix.os }}
+          name: build-${{ matrix.os }}-${{ matrix.sanitizer }}
           path: build.tar
           retention-days: 1
 
@@ -84,10 +85,12 @@ jobs:
     if: needs.pre_job.outputs.should_skip != 'true'
     env:
       CC: clang
+      ASAN_OPTIONS: halt_on_error=1
       UBSAN_OPTIONS: halt_on_error=1
     strategy:
       matrix:
         os: [ubuntu-latest, macos-latest]
+        sanitizer: [undefined, address]
       fail-fast: false
     steps:
       - name: Checkout Yosys
@@ -136,7 +139,7 @@ jobs:
       - name: Download build artifact
         uses: actions/download-artifact@v4
         with:
-          name: build-${{ matrix.os }}
+          name: build-${{ matrix.os }}-${{ matrix.sanitizer }}
 
       - name: Uncompress build
         shell: bash
@@ -168,6 +171,7 @@ jobs:
     strategy:
       matrix:
         os: [ubuntu-latest]
+        sanitizer: [undefined, address]
       fail-fast: false
     steps:
       - name: Checkout Yosys
@@ -181,7 +185,7 @@ jobs:
       - name: Download build artifact
         uses: actions/download-artifact@v4
         with:
-          name: build-${{ matrix.os }}
+          name: build-${{ matrix.os }}-${{ matrix.sanitizer }}
 
       - name: Uncompress build
         shell: bash

CHANGELOG

@@ -2,9 +2,16 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.54 .. Yosys 0.55-dev
+Yosys 0.55 .. Yosys 0.56-dev
 --------------------------
 
+Yosys 0.54 .. Yosys 0.55
+--------------------------
+ * Various
+    - read_verilog: Implemented SystemVerilog unique/priority if.
+    - "attrmap" pass is able to alter memory attributes.
+    - verific: Support SVA followed-by operator in cover mode.
+
 Yosys 0.53 .. Yosys 0.54
 --------------------------
  * New commands and options

Makefile

@@ -160,7 +160,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.54+0
+YOSYS_VER := 0.55+0
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)
@@ -183,7 +183,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline db72ec3.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 60f126c.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 

docs/source/cell/word_mux.rst

@@ -24,8 +24,8 @@ are zero, the value from ``A`` input is sent to the output. If the :math:`n`\
 'th bit from ``S`` is set, the value :math:`n`\ 'th ``WIDTH`` bits wide slice of
 the ``B`` input is sent to the output. When more than one bit from ``S`` is set
 the output is undefined. Cells of this type are used to model "parallel cases"
-(defined by using the ``parallel_case`` attribute or detected by an
-optimization).
+(defined by using the ``parallel_case`` attribute, the ``unique`` or ``unique0``
+SystemVerilog keywords, or detected by an optimization).
 
 The `$tribuf` cell is used to implement tristate logic. Cells of this type have
 a ``WIDTH`` parameter and inputs ``A`` and ``EN`` and an output ``Y``. The ``A``

docs/source/conf.py

@@ -6,7 +6,7 @@
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2025 YosysHQ GmbH'
-yosys_ver = "0.54"
+yosys_ver = "0.55"
 
 # select HTML theme
 html_theme = 'furo-ys'

docs/source/yosys_internals/verilog.rst

@@ -377,7 +377,7 @@ from SystemVerilog:
 - Assignments within expressions are supported.
 
 - The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
-  accepted on ``if`` and ``case`` conditionals.  (Those keywords are currently
-  handled in the same way as their equivalent ``full_case`` and
-  ``parallel_case`` attributes on ``case`` statements, and checked
-  for syntactic validity but otherwise ignored on ``if`` statements.)
+  supported on ``if`` and ``case`` conditionals.  (The Verilog frontend
+  will process conditionals using these keywords by annotating their
+  representation with the appropriate ``full_case`` and/or ``parallel_case``
+  attributes, which are described above.)

frontends/verific/verific.cc

@@ -3465,11 +3465,13 @@ struct VerificPass : public Pass {
 			RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
 			RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1);
+			RuntimeFlags::SetVar("veri_replace_const_exprs", 1);
 #endif
 #ifdef VERIFIC_VHDL_SUPPORT
 			RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
 			RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1);
+			RuntimeFlags::SetVar("vhdl_replace_const_exprs", 1);
 
 			RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
 			RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);

frontends/verific/verificsva.cc

@@ -1613,15 +1613,18 @@ struct VerificSvaImporter
 		}
 		else
 		if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||
-				inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)
+				inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION ||
+				(mode_cover && (
+					inst->Type() == PRIM_SVA_OVERLAPPED_FOLLOWED_BY ||
+					inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)))
 		{
 			Net *antecedent_net = inst->GetInput1();
 			Net *consequent_net = inst->GetInput2();
 			int node;
 
 			SvaFsm antecedent_fsm(clocking, trig);
 			node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net);
-			if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) {
+			if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION || inst->Type() == PRIM_SVA_NON_OVERLAPPED_FOLLOWED_BY) {
 				int next_node = antecedent_fsm.createNode();
 				antecedent_fsm.createEdge(node, next_node);
 				node = next_node;

frontends/verilog/verilog_frontend.cc

@@ -753,7 +753,7 @@ struct VerilogFileList : public Pass {
 			break;
 		}
 
-		extra_args(args, argidx, design);
+		extra_args(args, argidx, design, false);
 	}
 } VerilogFilelist;