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TheRealMDoerrTheRealMDoerr
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Restore VSR0-31. Removal had caused unsupported outgoing calling sequence.
1 parent 8857a21 commit d3db0b2

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‎src/hotspot/cpu/ppc/ppc.ad‎

Lines changed: 193 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,165 @@ register %{
258258
// Vector-Scalar Registers
259259
// ----------------------------
260260
// 1st 32 VSRs are aliases for the FPRs which are already defined above.
261+
reg_def VSR0 (SOC, SOC, Op_VecX, 0, VMRegImpl::Bad());
262+
reg_def VSR0_H (SOC, SOC, Op_VecX, 0, VMRegImpl::Bad());
263+
reg_def VSR0_J (SOC, SOC, Op_VecX, 0, VMRegImpl::Bad());
264+
reg_def VSR0_K (SOC, SOC, Op_VecX, 0, VMRegImpl::Bad());
265+
266+
reg_def VSR1 (SOC, SOC, Op_VecX, 1, VMRegImpl::Bad());
267+
reg_def VSR1_H (SOC, SOC, Op_VecX, 1, VMRegImpl::Bad());
268+
reg_def VSR1_J (SOC, SOC, Op_VecX, 1, VMRegImpl::Bad());
269+
reg_def VSR1_K (SOC, SOC, Op_VecX, 1, VMRegImpl::Bad());
270+
271+
reg_def VSR2 (SOC, SOC, Op_VecX, 2, VMRegImpl::Bad());
272+
reg_def VSR2_H (SOC, SOC, Op_VecX, 2, VMRegImpl::Bad());
273+
reg_def VSR2_J (SOC, SOC, Op_VecX, 2, VMRegImpl::Bad());
274+
reg_def VSR2_K (SOC, SOC, Op_VecX, 2, VMRegImpl::Bad());
275+
276+
reg_def VSR3 (SOC, SOC, Op_VecX, 3, VMRegImpl::Bad());
277+
reg_def VSR3_H (SOC, SOC, Op_VecX, 3, VMRegImpl::Bad());
278+
reg_def VSR3_J (SOC, SOC, Op_VecX, 3, VMRegImpl::Bad());
279+
reg_def VSR3_K (SOC, SOC, Op_VecX, 3, VMRegImpl::Bad());
280+
281+
reg_def VSR4 (SOC, SOC, Op_VecX, 4, VMRegImpl::Bad());
282+
reg_def VSR4_H (SOC, SOC, Op_VecX, 4, VMRegImpl::Bad());
283+
reg_def VSR4_J (SOC, SOC, Op_VecX, 4, VMRegImpl::Bad());
284+
reg_def VSR4_K (SOC, SOC, Op_VecX, 4, VMRegImpl::Bad());
285+
286+
reg_def VSR5 (SOC, SOC, Op_VecX, 5, VMRegImpl::Bad());
287+
reg_def VSR5_H (SOC, SOC, Op_VecX, 5, VMRegImpl::Bad());
288+
reg_def VSR5_J (SOC, SOC, Op_VecX, 5, VMRegImpl::Bad());
289+
reg_def VSR5_K (SOC, SOC, Op_VecX, 5, VMRegImpl::Bad());
290+
291+
reg_def VSR6 (SOC, SOC, Op_VecX, 6, VMRegImpl::Bad());
292+
reg_def VSR6_H (SOC, SOC, Op_VecX, 6, VMRegImpl::Bad());
293+
reg_def VSR6_J (SOC, SOC, Op_VecX, 6, VMRegImpl::Bad());
294+
reg_def VSR6_K (SOC, SOC, Op_VecX, 6, VMRegImpl::Bad());
295+
296+
reg_def VSR7 (SOC, SOC, Op_VecX, 7, VMRegImpl::Bad());
297+
reg_def VSR7_H (SOC, SOC, Op_VecX, 7, VMRegImpl::Bad());
298+
reg_def VSR7_J (SOC, SOC, Op_VecX, 7, VMRegImpl::Bad());
299+
reg_def VSR7_K (SOC, SOC, Op_VecX, 7, VMRegImpl::Bad());
300+
301+
reg_def VSR8 (SOC, SOC, Op_VecX, 8, VMRegImpl::Bad());
302+
reg_def VSR8_H (SOC, SOC, Op_VecX, 8, VMRegImpl::Bad());
303+
reg_def VSR8_J (SOC, SOC, Op_VecX, 8, VMRegImpl::Bad());
304+
reg_def VSR8_K (SOC, SOC, Op_VecX, 8, VMRegImpl::Bad());
305+
306+
reg_def VSR9 (SOC, SOC, Op_VecX, 9, VMRegImpl::Bad());
307+
reg_def VSR9_H (SOC, SOC, Op_VecX, 9, VMRegImpl::Bad());
308+
reg_def VSR9_J (SOC, SOC, Op_VecX, 9, VMRegImpl::Bad());
309+
reg_def VSR9_K (SOC, SOC, Op_VecX, 9, VMRegImpl::Bad());
310+
311+
reg_def VSR10 (SOC, SOC, Op_VecX, 10, VMRegImpl::Bad());
312+
reg_def VSR10_H(SOC, SOC, Op_VecX, 10, VMRegImpl::Bad());
313+
reg_def VSR10_J(SOC, SOC, Op_VecX, 10, VMRegImpl::Bad());
314+
reg_def VSR10_K(SOC, SOC, Op_VecX, 10, VMRegImpl::Bad());
315+
316+
reg_def VSR11 (SOC, SOC, Op_VecX, 11, VMRegImpl::Bad());
317+
reg_def VSR11_H(SOC, SOC, Op_VecX, 11, VMRegImpl::Bad());
318+
reg_def VSR11_J(SOC, SOC, Op_VecX, 11, VMRegImpl::Bad());
319+
reg_def VSR11_K(SOC, SOC, Op_VecX, 11, VMRegImpl::Bad());
320+
321+
reg_def VSR12 (SOC, SOC, Op_VecX, 12, VMRegImpl::Bad());
322+
reg_def VSR12_H(SOC, SOC, Op_VecX, 12, VMRegImpl::Bad());
323+
reg_def VSR12_J(SOC, SOC, Op_VecX, 12, VMRegImpl::Bad());
324+
reg_def VSR12_K(SOC, SOC, Op_VecX, 12, VMRegImpl::Bad());
325+
326+
reg_def VSR13 (SOC, SOC, Op_VecX, 13, VMRegImpl::Bad());
327+
reg_def VSR13_H(SOC, SOC, Op_VecX, 13, VMRegImpl::Bad());
328+
reg_def VSR13_J(SOC, SOC, Op_VecX, 13, VMRegImpl::Bad());
329+
reg_def VSR13_K(SOC, SOC, Op_VecX, 13, VMRegImpl::Bad());
330+
331+
reg_def VSR14 (SOC, SOC, Op_VecX, 14, VMRegImpl::Bad());
332+
reg_def VSR14_H(SOC, SOC, Op_VecX, 14, VMRegImpl::Bad());
333+
reg_def VSR14_J(SOC, SOC, Op_VecX, 14, VMRegImpl::Bad());
334+
reg_def VSR14_K(SOC, SOC, Op_VecX, 14, VMRegImpl::Bad());
335+
336+
reg_def VSR15 (SOC, SOC, Op_VecX, 15, VMRegImpl::Bad());
337+
reg_def VSR15_H(SOC, SOC, Op_VecX, 15, VMRegImpl::Bad());
338+
reg_def VSR15_J(SOC, SOC, Op_VecX, 15, VMRegImpl::Bad());
339+
reg_def VSR15_K(SOC, SOC, Op_VecX, 15, VMRegImpl::Bad());
340+
341+
reg_def VSR16 (SOC, SOC, Op_VecX, 16, VMRegImpl::Bad());
342+
reg_def VSR16_H(SOC, SOC, Op_VecX, 16, VMRegImpl::Bad());
343+
reg_def VSR16_J(SOC, SOC, Op_VecX, 16, VMRegImpl::Bad());
344+
reg_def VSR16_K(SOC, SOC, Op_VecX, 16, VMRegImpl::Bad());
345+
346+
reg_def VSR17 (SOC, SOC, Op_VecX, 17, VMRegImpl::Bad());
347+
reg_def VSR17_H(SOC, SOC, Op_VecX, 17, VMRegImpl::Bad());
348+
reg_def VSR17_J(SOC, SOC, Op_VecX, 17, VMRegImpl::Bad());
349+
reg_def VSR17_K(SOC, SOC, Op_VecX, 17, VMRegImpl::Bad());
350+
351+
reg_def VSR18 (SOC, SOC, Op_VecX, 18, VMRegImpl::Bad());
352+
reg_def VSR18_H(SOC, SOC, Op_VecX, 18, VMRegImpl::Bad());
353+
reg_def VSR18_J(SOC, SOC, Op_VecX, 18, VMRegImpl::Bad());
354+
reg_def VSR18_K(SOC, SOC, Op_VecX, 18, VMRegImpl::Bad());
355+
356+
reg_def VSR19 (SOC, SOC, Op_VecX, 19, VMRegImpl::Bad());
357+
reg_def VSR19_H(SOC, SOC, Op_VecX, 19, VMRegImpl::Bad());
358+
reg_def VSR19_J(SOC, SOC, Op_VecX, 19, VMRegImpl::Bad());
359+
reg_def VSR19_K(SOC, SOC, Op_VecX, 19, VMRegImpl::Bad());
360+
361+
reg_def VSR20 (SOC, SOC, Op_VecX, 20, VMRegImpl::Bad());
362+
reg_def VSR20_H(SOC, SOC, Op_VecX, 20, VMRegImpl::Bad());
363+
reg_def VSR20_J(SOC, SOC, Op_VecX, 20, VMRegImpl::Bad());
364+
reg_def VSR20_K(SOC, SOC, Op_VecX, 20, VMRegImpl::Bad());
365+
366+
reg_def VSR21 (SOC, SOC, Op_VecX, 21, VMRegImpl::Bad());
367+
reg_def VSR21_H(SOC, SOC, Op_VecX, 21, VMRegImpl::Bad());
368+
reg_def VSR21_J(SOC, SOC, Op_VecX, 21, VMRegImpl::Bad());
369+
reg_def VSR21_K(SOC, SOC, Op_VecX, 21, VMRegImpl::Bad());
370+
371+
reg_def VSR22 (SOC, SOC, Op_VecX, 22, VMRegImpl::Bad());
372+
reg_def VSR22_H(SOC, SOC, Op_VecX, 22, VMRegImpl::Bad());
373+
reg_def VSR22_J(SOC, SOC, Op_VecX, 22, VMRegImpl::Bad());
374+
reg_def VSR22_K(SOC, SOC, Op_VecX, 22, VMRegImpl::Bad());
375+
376+
reg_def VSR23 (SOC, SOC, Op_VecX, 23, VMRegImpl::Bad());
377+
reg_def VSR23_H(SOC, SOC, Op_VecX, 23, VMRegImpl::Bad());
378+
reg_def VSR23_J(SOC, SOC, Op_VecX, 23, VMRegImpl::Bad());
379+
reg_def VSR23_K(SOC, SOC, Op_VecX, 23, VMRegImpl::Bad());
380+
381+
reg_def VSR24 (SOC, SOC, Op_VecX, 24, VMRegImpl::Bad());
382+
reg_def VSR24_H(SOC, SOC, Op_VecX, 24, VMRegImpl::Bad());
383+
reg_def VSR24_J(SOC, SOC, Op_VecX, 24, VMRegImpl::Bad());
384+
reg_def VSR24_K(SOC, SOC, Op_VecX, 24, VMRegImpl::Bad());
385+
386+
reg_def VSR25 (SOC, SOC, Op_VecX, 25, VMRegImpl::Bad());
387+
reg_def VSR25_H(SOC, SOC, Op_VecX, 25, VMRegImpl::Bad());
388+
reg_def VSR25_J(SOC, SOC, Op_VecX, 25, VMRegImpl::Bad());
389+
reg_def VSR25_K(SOC, SOC, Op_VecX, 25, VMRegImpl::Bad());
390+
391+
reg_def VSR26 (SOC, SOC, Op_VecX, 26, VMRegImpl::Bad());
392+
reg_def VSR26_H(SOC, SOC, Op_VecX, 26, VMRegImpl::Bad());
393+
reg_def VSR26_J(SOC, SOC, Op_VecX, 26, VMRegImpl::Bad());
394+
reg_def VSR26_K(SOC, SOC, Op_VecX, 26, VMRegImpl::Bad());
395+
396+
reg_def VSR27 (SOC, SOC, Op_VecX, 27, VMRegImpl::Bad());
397+
reg_def VSR27_H(SOC, SOC, Op_VecX, 27, VMRegImpl::Bad());
398+
reg_def VSR27_J(SOC, SOC, Op_VecX, 27, VMRegImpl::Bad());
399+
reg_def VSR27_K(SOC, SOC, Op_VecX, 27, VMRegImpl::Bad());
400+
401+
reg_def VSR28 (SOC, SOC, Op_VecX, 28, VMRegImpl::Bad());
402+
reg_def VSR28_H(SOC, SOC, Op_VecX, 28, VMRegImpl::Bad());
403+
reg_def VSR28_J(SOC, SOC, Op_VecX, 28, VMRegImpl::Bad());
404+
reg_def VSR28_K(SOC, SOC, Op_VecX, 28, VMRegImpl::Bad());
405+
406+
reg_def VSR29 (SOC, SOC, Op_VecX, 29, VMRegImpl::Bad());
407+
reg_def VSR29_H(SOC, SOC, Op_VecX, 29, VMRegImpl::Bad());
408+
reg_def VSR29_J(SOC, SOC, Op_VecX, 29, VMRegImpl::Bad());
409+
reg_def VSR29_K(SOC, SOC, Op_VecX, 29, VMRegImpl::Bad());
410+
411+
reg_def VSR30 (SOC, SOC, Op_VecX, 30, VMRegImpl::Bad());
412+
reg_def VSR30_H(SOC, SOC, Op_VecX, 30, VMRegImpl::Bad());
413+
reg_def VSR30_J(SOC, SOC, Op_VecX, 30, VMRegImpl::Bad());
414+
reg_def VSR30_K(SOC, SOC, Op_VecX, 30, VMRegImpl::Bad());
415+
416+
reg_def VSR31 (SOC, SOC, Op_VecX, 31, VMRegImpl::Bad());
417+
reg_def VSR31_H(SOC, SOC, Op_VecX, 31, VMRegImpl::Bad());
418+
reg_def VSR31_J(SOC, SOC, Op_VecX, 31, VMRegImpl::Bad());
419+
reg_def VSR31_K(SOC, SOC, Op_VecX, 31, VMRegImpl::Bad());
261420

262421
// 2nd 32 VSRs are aliases for the VRs which are only defined here.
263422
reg_def VSR32 (SOC, SOC, Op_VecX, 32, VSR32->as_VMReg() );
@@ -550,6 +709,38 @@ alloc_class chunk2 (
550709
);
551710

552711
alloc_class chunk3 (
712+
VSR0 , VSR0_H , VSR0_J , VSR0_K ,
713+
VSR1 , VSR1_H , VSR1_J , VSR1_K ,
714+
VSR2 , VSR2_H , VSR2_J , VSR2_K ,
715+
VSR3 , VSR3_H , VSR3_J , VSR3_K ,
716+
VSR4 , VSR4_H , VSR4_J , VSR4_K ,
717+
VSR5 , VSR5_H , VSR5_J , VSR5_K ,
718+
VSR6 , VSR6_H , VSR6_J , VSR6_K ,
719+
VSR7 , VSR7_H , VSR7_J , VSR7_K ,
720+
VSR8 , VSR8_H , VSR8_J , VSR8_K ,
721+
VSR9 , VSR9_H , VSR9_J , VSR9_K ,
722+
VSR10, VSR10_H, VSR10_J, VSR10_K,
723+
VSR11, VSR11_H, VSR11_J, VSR11_K,
724+
VSR12, VSR12_H, VSR12_J, VSR12_K,
725+
VSR13, VSR13_H, VSR13_J, VSR13_K,
726+
VSR14, VSR14_H, VSR14_J, VSR14_K,
727+
VSR15, VSR15_H, VSR15_J, VSR15_K,
728+
VSR16, VSR16_H, VSR16_J, VSR16_K,
729+
VSR17, VSR17_H, VSR17_J, VSR17_K,
730+
VSR18, VSR18_H, VSR18_J, VSR18_K,
731+
VSR19, VSR19_H, VSR19_J, VSR19_K,
732+
VSR20, VSR20_H, VSR20_J, VSR20_K,
733+
VSR21, VSR21_H, VSR21_J, VSR21_K,
734+
VSR22, VSR22_H, VSR22_J, VSR22_K,
735+
VSR23, VSR23_H, VSR23_J, VSR23_K,
736+
VSR24, VSR24_H, VSR24_J, VSR24_K,
737+
VSR25, VSR25_H, VSR25_J, VSR25_K,
738+
VSR26, VSR26_H, VSR26_J, VSR26_K,
739+
VSR27, VSR27_H, VSR27_J, VSR27_K,
740+
VSR28, VSR28_H, VSR28_J, VSR28_K,
741+
VSR29, VSR29_H, VSR29_J, VSR29_K,
742+
VSR30, VSR30_H, VSR30_J, VSR30_K,
743+
VSR31, VSR31_H, VSR31_J, VSR31_K,
553744
VSR32, VSR32_H, VSR32_J, VSR32_K,
554745
VSR33, VSR33_H, VSR33_J, VSR33_K,
555746
VSR34, VSR34_H, VSR34_J, VSR34_K,
@@ -1737,8 +1928,8 @@ static enum RC rc_class(OptoReg::Name reg) {
17371928

17381929
assert(OptoReg::is_stack(reg) || reg >= 128+8, "flags are not expected");
17391930

1740-
// We have 32 vector registers (vector-scalar register 32-63), starting at index 136.
1741-
if (reg < 136+128) return rc_vs;
1931+
// We have 64 vector-scalar registers, starting at index 136.
1932+
if (reg < 136+256) return rc_vs;
17421933

17431934
// Special purpose registers are not allocated. We only accept stack from here.
17441935
assert(OptoReg::is_stack(reg), "what else is it?");

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