fix: fsd, fsw have reversed operands

ThinkOpenly · ThinkOpenly · commit 3c4bdfd96577 · 2025-06-11T07:08:41.000-05:00
diff --git a/model/riscv_insts_zcd.sail b/model/riscv_insts_zcd.sail
@@ -76,5 +76,5 @@ function clause execute (C_FSD(uimm, rsc1, rsc2)) = {
 
 mapping clause assembly = C_FSD(uimm, rsc1, rsc2)
       if (xlen == 32 | xlen == 64)
-  <-> "c.fsd" ^ spc() ^ creg_name(rsc1) ^ sep() ^ hex_bits_8(uimm @ 0b000) ^ "(" ^ creg_name(rsc2) ^ ")"
+  <-> "c.fsd" ^ spc() ^ creg_name(rsc2) ^ sep() ^ hex_bits_8(uimm @ 0b000) ^ "(" ^ creg_name(rsc1) ^ ")"
       if (xlen == 32 | xlen == 64)
diff --git a/model/riscv_insts_zcf.sail b/model/riscv_insts_zcf.sail
@@ -72,5 +72,5 @@ function clause execute (C_FSW(uimm, rsc1, rsc2)) = {
 }
 
 mapping clause assembly = C_FSW(uimm, rsc1, rsc2)
-  <-> "c.fsw" ^ spc() ^ creg_name(rsc1) ^ sep() ^ hex_bits_7(uimm @ 0b00) ^ "(" ^ creg_name(rsc2) ^ ")"
+  <-> "c.fsw" ^ spc() ^ creg_name(rsc2) ^ sep() ^ hex_bits_7(uimm @ 0b00) ^ "(" ^ creg_name(rsc1) ^ ")"
   when xlen == 32

Original file line number	Diff line number	Diff line change
`@@ -72,5 +72,5 @@ function clause execute (C_FSW(uimm, rsc1, rsc2)) = {`
`72`	`72`	`}`
`73`	`73`
`74`	`74`	`mapping clause assembly = C_FSW(uimm, rsc1, rsc2)`
`75`		`- <-> "c.fsw" ^ spc() ^ creg_name(rsc1) ^ sep() ^ hex_bits_7(uimm @ 0b00) ^ "(" ^ creg_name(rsc2) ^ ")"`
	`75`	`+ <-> "c.fsw" ^ spc() ^ creg_name(rsc2) ^ sep() ^ hex_bits_7(uimm @ 0b00) ^ "(" ^ creg_name(rsc1) ^ ")"`
`76`	`76`	`when xlen == 32`