crossbar-model-spice

Main schematic and model files:

• main_MST_crossbar_2x2.sch (run this file)
• model-mst.lib (link this file to the MST model in the schematic)
• there are other .sch files for logic gates, multiplexers, decoders and counters.

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Architecture

The objective of this repository is to implement an MST Crossbar Model schematic in PSICE/Qucs capable of storing a programmable input matrix and performing matrix–vector multiplication upon application of an input vector. The crossbar array consists of four programmable MST devices physically organized in a 2×2 grid.

Row Lines:

Each row is defined by a Top-Gate line and a corresponding Source line, shared across the MSTs in that row. Thus, two top-gate lines and two source lines span the two rows.

Column Lines:

Each column is defined by a dedicated Drain line, shared across the MSTs in that column. Two drain lines span the two columns.

Dual-MST Pairing:

Every functional MST cell is implemented as a dual-MST pair.

• The primary MST stores the programmable conductance state corresponding to the matrix element.
• The companion MST is fixed at a baseline conductance state and is used as a reference.
• Drain currents from the primary and companion MSTs are differentially combined at the transimpedance amplifier (TIA), enabling the representation of signed weights. Negative effective values are realized by subtracting the baseline current from the active MST current.

This organization allows the 2×2 crossbar to store a 2×2 weight matrix, supporting signed arithmetic while maintaining synchronous row–column addressing through the control logic.

The crossbar operates synchronously with a global clock (CLK) and supports two distinct modes:

• Write (W): Programs the crossbar with matrix elements.
• Read (R): Performs matrix–vector multiplication and retrieves results.

All operations are clock-synchronized with 10 ms pulse cycles (10 ms high, 10 ms low).

The external interface consists of:

• Inputs:
  • CLK – Global system clock
  • Write (W) – Write mode enable
  • Read (R) – Read mode enable
  • Write_Data Bus – Input bus carrying ±5 V programming pulses for conductance updates
  • Vector Input Bus – Input bus providing vector elements during read
• Outputs:
  • Result Output Bus – Captures output vector values after matrix–vector multiplication

All buses are multi-bit parallel lines (sub-lines) to support higher dimensional data throughput.

Detailed Documentation: https://docs.google.com/document/d/1Cc4gR0DjS_AqTyQnRPxK-RzZz9MakuBL0aNtFvNHA0Y