doc: updated dse compile doc

Author: Ed-5100

docs/tutorial/floorplan_dse_compile.rst

@@ -25,7 +25,7 @@ solutions.
 After generating the floorplan solutions, you can compile the project with a specific
 floorplan solution with the ``tapa compile`` command by specifying the ``--floorplan-path`` option.
 The application will be reorganized according to the floorplan solution, and pipeline
-will be added.
+will be added. An xo file and floorplan constrain xdc file will be generated.
 
 .. code-block:: bash
 
@@ -52,3 +52,43 @@ and add pipeline to the project for each floorplan solution generated.
         --clock-period 3.00 \
         --part-num xcu55c-fsvh2892-2L-e \
         --pipeline-config pipeline_config.json
+
+The ``--floorplan-config`` option specifies the floorplan DSE configuration file.
+An example of a floorplan DSE configuration file is as follows:
+
+.. code-block:: json
+
+    {
+        "max_seconds": 1000,
+        "dse_range_min": 0.7,
+        "dse_range_max": 0.88,
+        "partition_strategy": "flat",
+        "cell_pre_assignments": {},
+        "cpp_arg_pre_assignments": {
+            "a": "SLOT_X1Y0:SLOT_X1Y0",
+            "b_0": "SLOT_X2Y0:SLOT_X2Y0",
+            "b_1": "SLOT_X2Y0:SLOT_X2Y0",
+            "c_.*": "SLOT_X2Y0:SLOT_X2Y0"
+        },
+        "sys_port_pre_assignments": {
+            "ap_clk": "SLOT_X2Y0:SLOT_X2Y0",
+            "ap_rst_n": "SLOT_X2Y0:SLOT_X2Y0",
+            "interrupt": "SLOT_X2Y0:SLOT_X2Y0",
+            "s_axi_control_.*": "SLOT_X2Y1:SLOT_X2Y1"
+        },
+        "grouping_constraints": [],
+        "reserved_slot_to_cells": {},
+        "partition_schedule": [],
+        "slot_to_rtype_to_min_limit": {
+            "SLOT_X0Y2:SLOT_X0Y2": {
+            "LUT": 0.85
+            }
+        },
+        "slot_to_rtype_to_max_limit": {},
+        "ignore_narrow_edge_threshold": 1
+    }
+
+The ``cpp_arg_pre_assignments`` field specifies the pre-assignments of the C++ top function
+arguments to the slots. If the top port is an array, you can either specify each element
+individually or use a regex pattern to match the elements. ``sys_port_pre_assignments`` specifies
+the pre-assignments of the verilog system ports to the slots.