Update unit tester for verilog input

Author: mdko

tests/test_importexport.py

@@ -1648,6 +1648,11 @@ def test_existing_reset_wire_without_add_reset(self):
 
 class TestVerilogInput(unittest.TestCase):
     def setUp(self):
+        import subprocess
+        try:
+            version = subprocess.check_output(['yosys', '--version'])
+        except OSError:
+            raise unittest.SkipTest('Testing Verilog input requires yosys')
         pyrtl.reset_working_block()
 
     def test_import_counter(self):