Merge branch 'development' of https://github.com/UCSBarchlab/PyRTL into development

Author: timsherwood

docs/analysis.rst

@@ -18,7 +18,7 @@ Estimation
 
 .. .. _estimate-ref:
 
-.. automodule:: pyrtl.analysis.estimate
+.. automodule:: pyrtl.analysis
    :members:
    :show-inheritance:
    :special-members:

docs/export.rst

@@ -6,31 +6,31 @@ Exporting and Importing Designs
 Exporting Hardware Designs
 --------------------------
 
-.. autofunction:: pyrtl.verilog.output_to_verilog
+.. autofunction:: pyrtl.importexport.output_to_verilog
 
-.. autofunction:: pyrtl.inputoutput.output_to_firrtl
+.. autofunction:: pyrtl.importexport.output_to_firrtl
 
 Exporting Testbenches
 ------------------------
 
-.. autofunction:: pyrtl.verilog.output_verilog_testbench
+.. autofunction:: pyrtl.importexport.output_verilog_testbench
 
 
 Importing Verilog
 -----------------
 
-.. autofunction:: pyrtl.inputoutput.input_from_blif
+.. autofunction:: pyrtl.importexport.input_from_blif
 
 
 Outputting for Visualization
 ---------------------------
 
-.. autofunction:: pyrtl.inputoutput.output_to_trivialgraph
-.. autofunction:: pyrtl.inputoutput.output_to_graphviz
-.. autofunction:: pyrtl.inputoutput.graphviz_detailed_namer
-.. autofunction:: pyrtl.inputoutput.output_to_svg
-.. autofunction:: pyrtl.inputoutput.block_to_graphviz_string
-.. autofunction:: pyrtl.inputoutput.block_to_svg
-.. autofunction:: pyrtl.inputoutput.trace_to_html
-.. autofunction:: pyrtl.inputoutput.net_graph
+.. autofunction:: pyrtl.visualization.output_to_trivialgraph
+.. autofunction:: pyrtl.visualization.output_to_graphviz
+.. autofunction:: pyrtl.visualization.graphviz_detailed_namer
+.. autofunction:: pyrtl.visualization.output_to_svg
+.. autofunction:: pyrtl.visualization.block_to_graphviz_string
+.. autofunction:: pyrtl.visualization.block_to_svg
+.. autofunction:: pyrtl.visualization.trace_to_html
+.. autofunction:: pyrtl.visualization.net_graph
 

examples/example7-synth-timing-draft.py

@@ -8,7 +8,6 @@
 
 
 import pyrtl
-from pyrtl.analysis import estimate
 
 # --- Part 1: Timing Analysis ------------------------------------------------
 
@@ -27,7 +26,7 @@
 
 # Generating timing analysis information
 print("Pre Synthesis:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 
 # We are also able to print out the critical paths as well as get them
@@ -39,7 +38,7 @@
 # PyRTL also provides estimates for the area that would be used up if the
 # circuit was printed as an ASIC.
 
-logic_area, mem_area = estimate.area_estimation(tech_in_nm=65)
+logic_area, mem_area = pyrtl.area_estimation(tech_in_nm=65)
 est_area = logic_area + mem_area
 print("Estimated Area of block", est_area, "sq mm")
 print()
@@ -58,7 +57,7 @@
 pyrtl.synthesize()
 
 print("Pre Optimization:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 for net in pyrtl.working_block().logic:
     print(str(net))
@@ -73,7 +72,7 @@
 
 # Now to see the difference
 print("Post Optimization:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 
 for net in pyrtl.working_block().logic:

pyrtl/__init__.py

@@ -20,14 +20,14 @@
 from .wire import Register
 
 # helper functions
-
 from .helperfuncs import input_list
 from .helperfuncs import output_list
 from .helperfuncs import register_list
 from .helperfuncs import wirevector_list
 from .helperfuncs import log2
 from .helperfuncs import truncate
 from .helperfuncs import match_bitpattern
+from .helperfuncs import bitpattern_to_val
 from .helperfuncs import chop
 from .helperfuncs import val_to_signed_integer
 from .helperfuncs import val_to_formatted_str
@@ -66,7 +66,6 @@
 from .corecircuits import shift_left_logical
 from .corecircuits import shift_right_logical
 
-
 # memory blocks
 from .memory import MemBlock
 from .memory import RomBlock
@@ -82,24 +81,24 @@
 from .simulation import SimulationTrace
 from .compilesim import CompiledSimulation
 
-# input and output to file format routines
-from .inputoutput import input_from_blif
-from .inputoutput import output_to_trivialgraph
-from .inputoutput import graphviz_detailed_namer
-from .inputoutput import output_to_graphviz
-from .inputoutput import output_to_svg
-from .inputoutput import output_to_firrtl
-from .inputoutput import block_to_graphviz_string
-from .inputoutput import block_to_svg
-from .inputoutput import trace_to_html
-from .inputoutput import net_graph
+# block visualization output formats
+from .visualization import output_to_trivialgraph
+from .visualization import graphviz_detailed_namer
+from .visualization import output_to_graphviz
+from .visualization import output_to_svg
+from .visualization import block_to_graphviz_string
+from .visualization import block_to_svg
+from .visualization import trace_to_html
+from .visualization import net_graph
 
-# extraction to verilog and verilog testbench
-from .verilog import output_to_verilog
-from .verilog import OutputToVerilog
-from .verilog import output_verilog_testbench
+# import from and export to file format routines
+from .importexport import output_to_verilog
+from .importexport import OutputToVerilog
+from .importexport import output_verilog_testbench
+from .importexport import input_from_blif
+from .importexport import output_to_firrtl
 
-# different analysis and transform passes
+# different transform passes
 from .passes import common_subexp_elimination
 from .passes import constant_propagation
 from .passes import synthesize
@@ -109,4 +108,14 @@
 from .passes import one_bit_selects
 from .passes import two_way_concat
 
-from .transform import net_transform, wire_transform, replace_wire, copy_block, clone_wire
+from .transform import net_transform
+from .transform import wire_transform
+from .transform import copy_block
+from .transform import clone_wire
+from .transform import replace_wires
+from .transform import replace_wire_fast
+
+# analysis and estimation functions
+from .analysis import area_estimation
+from .analysis import TimingAnalysis
+from .analysis import yosys_area_delay

pyrtl/analysis/estimate.py renamed to pyrtl/analysis.py

@@ -13,12 +13,12 @@
 import subprocess
 import sys
 
-from ..core import working_block
-from ..wire import Input, Const, Register
-from ..pyrtlexceptions import PyrtlError, PyrtlInternalError
-from ..verilog import output_to_verilog
-from ..memory import RomBlock
-from ..helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
+from .core import working_block
+from .wire import Input, Const, Register
+from .pyrtlexceptions import PyrtlError, PyrtlInternalError
+from .importexport import output_to_verilog
+from .memory import RomBlock
+from .helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
 
 
 # --------------------------------------------------------------------

pyrtl/analysis/__init__.py

@@ -34,7 +34,33 @@
 is a context manager (under which conditional assignements can be made), and "otherwise",
 which is an instance that stands in for a 'fall through' case.  The details of how these
 should be used, and the difference between normal assignments and condtional assignments,
-described in more detail in the state machine example from in prytl/examples.
+described in more detail in the state machine example in examples/example3-statemachine.py.
+
+There are instances where you might want a wirevector to be set to a certain value in all
+but certain with blocks. For example, say you have a processor with a PC register that is
+normally updated to PC + 1 after each cycle, except when the current instruction is
+a branch or jump. You could represent that as follows::
+
+    pc = pyrtl.Register(32)
+    instr = pyrtl.WireVector(32)
+    res = pyrtl.WireVector(32)
+
+    op = instr[:7]
+    ADD = 0b0110011
+    JMP = 0b1101111
+
+    with conditional_assignment(
+        defaults={
+            pc: pc + 1,
+            res: 0
+        }
+    ):
+        with op == ADD:
+            res |= instr[15:20] + instr[20:25]
+            # pc will be updated to pc + 1
+        with op == JMP:
+            pc.next |= pc + instr[7:]
+            # res will be set to 0
 
 In addition to the conditional context, there is a helper function "currently_under_condition"
 which will test if the code where it is called is currently elaborating hardware
@@ -67,6 +93,13 @@ def currently_under_condition():
 # instances (hopefully the only and unchanging instances) of the following two types.
 
 class _ConditionalAssignment(object):
+    def __init__(self):
+        self.defaults = {}
+
+    def __call__(self, defaults):
+        self.defaults = defaults
+        return self
+
     """ Context providing funcitionality of "conditional_assignment". """
     def __enter__(self):
         global _depth
@@ -75,7 +108,7 @@ def __enter__(self):
 
     def __exit__(self, *exc_info):
         try:
-            _finalize()
+            _finalize(self.defaults)
         finally:
             # even if the above finalization throws an error we need to
             # reset the state to prevent errors from bleeding over
@@ -181,7 +214,7 @@ def _pred_sets_are_in_conflict(pred_set_a, pred_set_b):
     return True
 
 
-def _finalize():
+def _finalize(defaults):
     """Build the required muxes and call back to WireVector to finalize the wirevector build."""
     from .memory import MemBlock
     from pyrtl.corecircuits import select
@@ -203,13 +236,13 @@ def _finalize():
         # handle wirevector and register assignments
         else:
             if isinstance(lhs, Register):
-                if hasattr(lhs, 'condition_default'):
-                    result = lhs.condition_default
+                if lhs in defaults:
+                    result = defaults[lhs]
                 else:
                     result = lhs  # default for registers is "self"
             elif isinstance(lhs, WireVector):
-                if hasattr(lhs, 'condition_default'):
-                    result = lhs.condition_default
+                if lhs in defaults:
+                    result = defaults[lhs]
                 else:
                     result = 0  # default for wire is "0"
             else:

pyrtl/conditional.py

@@ -460,7 +460,7 @@ def add_wire_dst(edge, node):
 
     def _repr_svg_(self):
         """ IPython display support for Block. """
-        from .inputoutput import block_to_svg
+        from .visualization import block_to_svg
         return block_to_svg(self)
 
     def __iter__(self):
@@ -730,11 +730,21 @@ def sanity_check_net(self, net):
 class PostSynthBlock(Block):
     """ This is a block with extra metadata required to maintain the
     pre-synthesis interface during post-synthesis.
+
+    It currently holds the following instance attributes:
+
+    * *.io_map*: a map from old IO wirevector to a list of new IO wirevectors it maps to;
+        this is a list because for unmerged io vectors, each old N-bit IO wirevector maps
+        to N new 1-bit IO wirevectors.
+    * *.reg_map*: a map from old register to a list of new registers; a list because post-synthesis,
+        each N-bit register has been mapped to N 1-bit registers
+    * *.mem_map*: a map from old memory block to the new memory block
     """
 
     def __init__(self):
         super(PostSynthBlock, self).__init__()
-        self.io_map = {}
+        self.io_map = collections.defaultdict(list)
+        self.reg_map = collections.defaultdict(list)
         self.mem_map = {}