Merge pull request #351 from pllab/cleanup_directories

Cleanup directories, consolidate and rename files.

Author: mdko

docs/analysis.rst

@@ -18,7 +18,7 @@ Estimation
 
 .. .. _estimate-ref:
 
-.. automodule:: pyrtl.analysis.estimate
+.. automodule:: pyrtl.analysis
    :members:
    :show-inheritance:
    :special-members:

docs/export.rst

@@ -6,31 +6,31 @@ Exporting and Importing Designs
 Exporting Hardware Designs
 --------------------------
 
-.. autofunction:: pyrtl.verilog.output_to_verilog
+.. autofunction:: pyrtl.importexport.output_to_verilog
 
-.. autofunction:: pyrtl.inputoutput.output_to_firrtl
+.. autofunction:: pyrtl.importexport.output_to_firrtl
 
 Exporting Testbenches
 ------------------------
 
-.. autofunction:: pyrtl.verilog.output_verilog_testbench
+.. autofunction:: pyrtl.importexport.output_verilog_testbench
 
 
 Importing Verilog
 -----------------
 
-.. autofunction:: pyrtl.inputoutput.input_from_blif
+.. autofunction:: pyrtl.importexport.input_from_blif
 
 
 Outputting for Visualization
 ---------------------------
 
-.. autofunction:: pyrtl.inputoutput.output_to_trivialgraph
-.. autofunction:: pyrtl.inputoutput.output_to_graphviz
-.. autofunction:: pyrtl.inputoutput.graphviz_detailed_namer
-.. autofunction:: pyrtl.inputoutput.output_to_svg
-.. autofunction:: pyrtl.inputoutput.block_to_graphviz_string
-.. autofunction:: pyrtl.inputoutput.block_to_svg
-.. autofunction:: pyrtl.inputoutput.trace_to_html
-.. autofunction:: pyrtl.inputoutput.net_graph
+.. autofunction:: pyrtl.visualization.output_to_trivialgraph
+.. autofunction:: pyrtl.visualization.output_to_graphviz
+.. autofunction:: pyrtl.visualization.graphviz_detailed_namer
+.. autofunction:: pyrtl.visualization.output_to_svg
+.. autofunction:: pyrtl.visualization.block_to_graphviz_string
+.. autofunction:: pyrtl.visualization.block_to_svg
+.. autofunction:: pyrtl.visualization.trace_to_html
+.. autofunction:: pyrtl.visualization.net_graph
 

examples/example7-synth-timing-draft.py

@@ -8,7 +8,6 @@
 
 
 import pyrtl
-from pyrtl.analysis import estimate
 
 # --- Part 1: Timing Analysis ------------------------------------------------
 
@@ -27,7 +26,7 @@
 
 # Generating timing analysis information
 print("Pre Synthesis:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 
 # We are also able to print out the critical paths as well as get them
@@ -39,7 +38,7 @@
 # PyRTL also provides estimates for the area that would be used up if the
 # circuit was printed as an ASIC.
 
-logic_area, mem_area = estimate.area_estimation(tech_in_nm=65)
+logic_area, mem_area = pyrtl.area_estimation(tech_in_nm=65)
 est_area = logic_area + mem_area
 print("Estimated Area of block", est_area, "sq mm")
 print()
@@ -58,7 +57,7 @@
 pyrtl.synthesize()
 
 print("Pre Optimization:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 for net in pyrtl.working_block().logic:
     print(str(net))
@@ -73,7 +72,7 @@
 
 # Now to see the difference
 print("Post Optimization:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 
 for net in pyrtl.working_block().logic:

pyrtl/__init__.py

@@ -20,7 +20,6 @@
 from .wire import Register
 
 # helper functions
-
 from .helperfuncs import input_list
 from .helperfuncs import output_list
 from .helperfuncs import register_list
@@ -67,7 +66,6 @@
 from .corecircuits import shift_left_logical
 from .corecircuits import shift_right_logical
 
-
 # memory blocks
 from .memory import MemBlock
 from .memory import RomBlock
@@ -83,24 +81,24 @@
 from .simulation import SimulationTrace
 from .compilesim import CompiledSimulation
 
-# input and output to file format routines
-from .inputoutput import input_from_blif
-from .inputoutput import output_to_trivialgraph
-from .inputoutput import graphviz_detailed_namer
-from .inputoutput import output_to_graphviz
-from .inputoutput import output_to_svg
-from .inputoutput import output_to_firrtl
-from .inputoutput import block_to_graphviz_string
-from .inputoutput import block_to_svg
-from .inputoutput import trace_to_html
-from .inputoutput import net_graph
+# block visualization output formats
+from .visualization import output_to_trivialgraph
+from .visualization import graphviz_detailed_namer
+from .visualization import output_to_graphviz
+from .visualization import output_to_svg
+from .visualization import block_to_graphviz_string
+from .visualization import block_to_svg
+from .visualization import trace_to_html
+from .visualization import net_graph
 
-# extraction to verilog and verilog testbench
-from .verilog import output_to_verilog
-from .verilog import OutputToVerilog
-from .verilog import output_verilog_testbench
+# import from and export to file format routines
+from .importexport import output_to_verilog
+from .importexport import OutputToVerilog
+from .importexport import output_verilog_testbench
+from .importexport import input_from_blif
+from .importexport import output_to_firrtl
 
-# different analysis and transform passes
+# different transform passes
 from .passes import common_subexp_elimination
 from .passes import constant_propagation
 from .passes import synthesize
@@ -116,3 +114,8 @@
 from .transform import clone_wire
 from .transform import replace_wires
 from .transform import replace_wire_fast
+
+# analysis and estimation functions
+from .analysis import area_estimation
+from .analysis import TimingAnalysis
+from .analysis import yosys_area_delay

pyrtl/analysis/estimate.py renamed to pyrtl/analysis.py

@@ -13,12 +13,12 @@
 import subprocess
 import sys
 
-from ..core import working_block
-from ..wire import Input, Const, Register
-from ..pyrtlexceptions import PyrtlError, PyrtlInternalError
-from ..verilog import output_to_verilog
-from ..memory import RomBlock
-from ..helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
+from .core import working_block
+from .wire import Input, Const, Register
+from .pyrtlexceptions import PyrtlError, PyrtlInternalError
+from .importexport import output_to_verilog
+from .memory import RomBlock
+from .helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
 
 
 # --------------------------------------------------------------------

pyrtl/analysis/__init__.py

@@ -460,7 +460,7 @@ def add_wire_dst(edge, node):
 
     def _repr_svg_(self):
         """ IPython display support for Block. """
-        from .inputoutput import block_to_svg
+        from .visualization import block_to_svg
         return block_to_svg(self)
 
     def __iter__(self):