rename inputoutput to importexport to reflect contents more clearly

Author: mdko

docs/export.rst

@@ -6,20 +6,20 @@ Exporting and Importing Designs
 Exporting Hardware Designs
 --------------------------
 
-.. autofunction:: pyrtl.inputoutput.output_to_verilog
+.. autofunction:: pyrtl.importexport.output_to_verilog
 
-.. autofunction:: pyrtl.inputoutput.output_to_firrtl
+.. autofunction:: pyrtl.importexport.output_to_firrtl
 
 Exporting Testbenches
 ------------------------
 
-.. autofunction:: pyrtl.inputoutput.output_verilog_testbench
+.. autofunction:: pyrtl.importexport.output_verilog_testbench
 
 
 Importing Verilog
 -----------------
 
-.. autofunction:: pyrtl.inputoutput.input_from_blif
+.. autofunction:: pyrtl.importexport.input_from_blif
 
 
 Outputting for Visualization

pyrtl/__init__.py

@@ -91,12 +91,12 @@
 from .visualization import trace_to_html
 from .visualization import net_graph
 
-# input and output to file format routines
-from .inputoutput import output_to_verilog
-from .inputoutput import OutputToVerilog
-from .inputoutput import output_verilog_testbench
-from .inputoutput import input_from_blif
-from .inputoutput import output_to_firrtl
+# import from and export to file format routines
+from .importexport import output_to_verilog
+from .importexport import OutputToVerilog
+from .importexport import output_verilog_testbench
+from .importexport import input_from_blif
+from .importexport import output_to_firrtl
 
 # different transform passes
 from .passes import common_subexp_elimination

pyrtl/analysis.py

@@ -16,7 +16,7 @@
 from .core import working_block
 from .wire import Input, Const, Register
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError
-from .inputoutput import output_to_verilog
+from .importexport import output_to_verilog
 from .memory import RomBlock
 from .helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
 

pyrtl/inputoutput.py renamed to pyrtl/importexport.py

@@ -1,5 +1,5 @@
 """
-Helper functions creating verilog implementations and testbenches.
+Helper functions for reading and writing hardware files.
 
 Each of the functions in inputoutput take a block and a file descriptor.
 The functions provided either read the file and update the Block
@@ -640,12 +640,6 @@ def _to_verilog_footer(file):
     print('endmodule\n', file=file)
 
 
-# ----------------------------------------------------------------
-#   ___  ___  __  ___  __   ___       __
-#    |  |__  /__`  |  |__) |__  |\ | /  ` |__|
-#    |  |___ .__/  |  |__) |___ | \| \__, |  |
-#
-
 def output_verilog_testbench(dest_file, simulation_trace=None, toplevel_include=None,
                              vcd="waveform.vcd", cmd=None, block=None):
     """ Output a Verilog testbench for the block/inputs used in the simulation trace.

pyrtl/simulation.py

@@ -12,7 +12,7 @@
 from .wire import Input, Register, Const, Output, WireVector
 from .memory import RomBlock
 from .helperfuncs import check_rtl_assertions, _currently_in_jupyter_notebook
-from .inputoutput import _VerilogSanitizer
+from .importexport import _VerilogSanitizer
 
 # ----------------------------------------------------------------
 #    __                         ___    __

pyrtl/visualization.py

@@ -1,9 +1,8 @@
 """
-Helper functions for reading and writing hardware files.
+Helper functions for viewing the block visually.
 
-Each of the functions in inputoutput take a block and a file descriptor.
-The functions provided either read the file and update the Block
-accordingly, or write information from the Block out to the file.
+Each of the functions in visualization take a block and a file descriptor.
+The functions provided write the block as a given visual format to the file.
 """
 
 from __future__ import print_function, unicode_literals
@@ -13,36 +12,6 @@
 from .wire import WireVector, Input, Output, Const, Register
 
 
-# -----------------------------------------------------------------
-#            __       ___
-#    | |\ | |__) |  |  |
-#    | | \| |    \__/  |
-
-# ----------------------------------------------------------------
-#    __       ___  __       ___
-#   /  \ |  |  |  |__) |  |  |
-#   \__/ \__/  |  |    \__/  |
-#
-
-
-def _trivialgraph_default_namer(thing, is_edge=True):
-    """ Returns a "good" string for thing in printed graphs. """
-    if is_edge:
-        if thing.name is None or thing.name.startswith('tmp'):
-            return ''
-        else:
-            return '/'.join([thing.name, str(len(thing))])
-    elif isinstance(thing, Const):
-        return str(thing.val)
-    elif isinstance(thing, WireVector):
-        return thing.name or '??'
-    else:
-        try:
-            return thing.op + str(thing.op_param or '')
-        except AttributeError:
-            raise PyrtlError('no naming rule for "%s"' % str(thing))
-
-
 def net_graph(block=None, split_state=False):
     """ Return a graph representation of the given block.
 
@@ -107,6 +76,29 @@ def net_graph(block=None, split_state=False):
     return graph
 
 
+# -----------------------------------------------------------------
+#    ___  __   ___
+#     |  / _` |___
+#     |  \__> |
+
+def _trivialgraph_default_namer(thing, is_edge=True):
+    """ Returns a "good" string for thing in printed graphs. """
+    if is_edge:
+        if thing.name is None or thing.name.startswith('tmp'):
+            return ''
+        else:
+            return '/'.join([thing.name, str(len(thing))])
+    elif isinstance(thing, Const):
+        return str(thing.val)
+    elif isinstance(thing, WireVector):
+        return thing.name or '??'
+    else:
+        try:
+            return thing.op + str(thing.op_param or '')
+        except AttributeError:
+            raise PyrtlError('no naming rule for "%s"' % str(thing))
+
+
 def output_to_trivialgraph(file, namer=_trivialgraph_default_namer, block=None, split_state=False):
     """ Walk the block and output it in trivial graph format to the open file.
 
@@ -139,6 +131,11 @@ def output_to_trivialgraph(file, namer=_trivialgraph_default_namer, block=None,
             print('%d %d %s' % (from_index, to_index, namer(edge)), file=file)
 
 
+# -----------------------------------------------------------------
+#     __   __   __   __              __
+#    / _` |__) |__| |__) |__| \  / |  /
+#    \__> |  \ |  | |    |  |  \/  | /__
+
 def _default_edge_namer(edge, is_to_splitmerge=False, extra_edge_info=None):
     """
     A function for naming an edge for use in the graphviz graph.
@@ -376,6 +373,11 @@ def block_to_graphviz_string(block=None, namer=_graphviz_default_namer, split_st
     return rstring
 
 
+# -----------------------------------------------------------------
+#     __        __
+#    /__` \  / / _`
+#    .__/  \/  \__>
+
 def output_to_svg(file, block=None, split_state=True):
     """ Output the block as an SVG to the open file.
 
@@ -400,6 +402,11 @@ def block_to_svg(block=None, split_state=True):
         raise PyrtlError('need graphviz installed (try "pip install graphviz")')
 
 
+# -----------------------------------------------------------------
+#         ___
+#    |__|  |  |\/| |
+#    |  |  |  |  | |___
+
 def trace_to_html(simtrace, trace_list=None, sortkey=None):
     """ Return a HTML block showing the trace.
 

tests/test_inputoutput.py renamed to tests/test_importexport.py

@@ -3,7 +3,7 @@
 import io
 import six
 import pyrtl
-from pyrtl.inputoutput import _VerilogSanitizer
+from pyrtl.importexport import _VerilogSanitizer
 from pyrtl.rtllib import testingutils as utils
 
 

tests/test_visualization.py

@@ -2,7 +2,7 @@
 import random
 import io
 import pyrtl
-from .test_inputoutput import full_adder_blif
+from .test_importexport import full_adder_blif
 
 
 graphviz_string = """