move estimate.py out of analysis directory, rename

Author: mdko

docs/analysis.rst

@@ -18,7 +18,7 @@ Estimation
 
 .. .. _estimate-ref:
 
-.. automodule:: pyrtl.analysis.estimate
+.. automodule:: pyrtl.analysis
    :members:
    :show-inheritance:
    :special-members:

examples/example7-synth-timing-draft.py

@@ -8,7 +8,6 @@
 
 
 import pyrtl
-from pyrtl.analysis import estimate
 
 # --- Part 1: Timing Analysis ------------------------------------------------
 
@@ -27,7 +26,7 @@
 
 # Generating timing analysis information
 print("Pre Synthesis:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 
 # We are also able to print out the critical paths as well as get them
@@ -39,7 +38,7 @@
 # PyRTL also provides estimates for the area that would be used up if the
 # circuit was printed as an ASIC.
 
-logic_area, mem_area = estimate.area_estimation(tech_in_nm=65)
+logic_area, mem_area = pyrtl.area_estimation(tech_in_nm=65)
 est_area = logic_area + mem_area
 print("Estimated Area of block", est_area, "sq mm")
 print()
@@ -58,7 +57,7 @@
 pyrtl.synthesize()
 
 print("Pre Optimization:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 for net in pyrtl.working_block().logic:
     print(str(net))
@@ -73,7 +72,7 @@
 
 # Now to see the difference
 print("Post Optimization:")
-timing = estimate.TimingAnalysis()
+timing = pyrtl.TimingAnalysis()
 timing.print_max_length()
 
 for net in pyrtl.working_block().logic:

pyrtl/__init__.py

@@ -98,7 +98,7 @@
 from .inputoutput import input_from_blif
 from .inputoutput import output_to_firrtl
 
-# different analysis and transform passes
+# different transform passes
 from .passes import common_subexp_elimination
 from .passes import constant_propagation
 from .passes import synthesize
@@ -114,3 +114,8 @@
 from .transform import clone_wire
 from .transform import replace_wires
 from .transform import replace_wire_fast
+
+# analysis and estimation functions
+from .analysis import area_estimation
+from .analysis import TimingAnalysis
+from .analysis import yosys_area_delay

pyrtl/analysis/estimate.py renamed to pyrtl/analysis.py

@@ -13,12 +13,12 @@
 import subprocess
 import sys
 
-from ..core import working_block
-from ..wire import Input, Const, Register
-from ..pyrtlexceptions import PyrtlError, PyrtlInternalError
-from ..inputoutput import output_to_verilog
-from ..memory import RomBlock
-from ..helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
+from .core import working_block
+from .wire import Input, Const, Register
+from .pyrtlexceptions import PyrtlError, PyrtlInternalError
+from .inputoutput import output_to_verilog
+from .memory import RomBlock
+from .helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
 
 
 # --------------------------------------------------------------------

pyrtl/analysis/__init__.py

@@ -1,11 +1,7 @@
 from __future__ import print_function, unicode_literals, absolute_import
-from .test_transform import NetWireNumTestCases
-from pyrtl.wire import Const, Output
-from pyrtl.analysis import estimate
 
 import unittest
 import pyrtl
-import io
 
 
 class TestAreaEstimate(unittest.TestCase):
@@ -41,7 +37,7 @@ def test_area_est_unchanged(self):
         atimesb <<= a * b
         memread <<= mem[0]
         mem[1] <<= a
-        self.assertEquals(estimate.area_estimation(), (0.00734386752, 0.01879779717361501))
+        self.assertEquals(pyrtl.area_estimation(), (0.00734386752, 0.01879779717361501))
 
     def test_area_est_unchanged_with_rom(self):
         a = pyrtl.Const(2, 8)
@@ -70,7 +66,7 @@ def test_area_est_unchanged_with_rom(self):
         bminusa <<= a - b
         atimesb <<= a * b
         memread <<= mem[reg]
-        self.assertEquals(estimate.area_estimation(), (0.00734386752, 0.001879779717361501))
+        self.assertEquals(pyrtl.area_estimation(), (0.00734386752, 0.001879779717361501))
 
 
 class TestTimingEstimate(unittest.TestCase):
@@ -106,7 +102,7 @@ def test_time_est_unchanged(self):
         atimesb <<= a * b
         memread <<= mem[0]
         mem[1] <<= a
-        timing = estimate.TimingAnalysis()
+        timing = pyrtl.TimingAnalysis()
         self.assertEqual(timing.max_freq(), 610.2770657878676)
         self.assertEquals(timing.max_length(), 1255.6000000000001)
 

tests/test_estimate.py renamed to tests/test_analysis.py

@@ -8,7 +8,6 @@
 
 import pyrtl
 from pyrtl.wire import Const, Output
-from pyrtl.analysis import estimate
 
 from .test_transform import NetWireNumTestCases
 
@@ -613,7 +612,7 @@ def everything_t_procedure(self, timing_val=None, opt_timing_val=None):
         # to make sure that the timing matches
         # this is a subprocess to do the synth and timing
         block = pyrtl.working_block()
-        timing = estimate.TimingAnalysis(block)
+        timing = pyrtl.TimingAnalysis(block)
         timing_max_length = timing.max_length()
         if timing_val is not None:
             self.assertEqual(timing_max_length, timing_val)
@@ -623,7 +622,7 @@ def everything_t_procedure(self, timing_val=None, opt_timing_val=None):
         pyrtl.optimize()
 
         block = pyrtl.working_block()
-        timing = estimate.TimingAnalysis(block)
+        timing = pyrtl.TimingAnalysis(block)
         timing_max_length = timing.max_length()
         if opt_timing_val is not None:
             self.assertEqual(timing_max_length, opt_timing_val)
@@ -633,7 +632,7 @@ def everything_t_procedure(self, timing_val=None, opt_timing_val=None):
         pyrtl.optimize()
 
         block = pyrtl.working_block()
-        timing = estimate.TimingAnalysis(block)
+        timing = pyrtl.TimingAnalysis(block)
         timing_max_length = timing.max_length()
         critical_path = timing.critical_path(print_cp=False)
         block = pyrtl.working_block()
@@ -644,7 +643,7 @@ def everything_t_procedure(self, timing_val=None, opt_timing_val=None):
         pyrtl.optimize()
 
         block = pyrtl.working_block()
-        timing = estimate.TimingAnalysis(block)
+        timing = pyrtl.TimingAnalysis(block)
         timing_max_length = timing.max_length()
         critical_path = timing.critical_path(print_cp=False)
         block.sanity_check()
@@ -687,7 +686,7 @@ def test_timing_error(self):
             pyrtl.synthesize()
             pyrtl.optimize()
             block = pyrtl.working_block()
-            _timing = estimate.TimingAnalysis(block)
+            _timing = pyrtl.TimingAnalysis(block)
         sys.stdout = sys.__stdout__
         self.assertTrue(output.getvalue().startswith("Loop found:"))
 
@@ -752,7 +751,7 @@ def test_two_way_concat(self):
         self.assertEqual(len(concat_nets), 1)
         self.assertEqual(concat_nets[0].args, (i, j, k))
 
-        pyrtl.passes.two_way_concat()
+        pyrtl.two_way_concat()
 
         concat_nets = list(block.logic_subset(op='c'))
         self.assertEqual(len(concat_nets), 2)
@@ -776,7 +775,7 @@ def test_one_bit_selects(self):
         self.assertEqual(len(select_nets), 1)
         self.assertEqual(tuple(select_nets[0].op_param), (0, 2, 4, 6, 8, 10))
 
-        pyrtl.passes.one_bit_selects()
+        pyrtl.one_bit_selects()
 
         select_nets = list(block.logic_subset(op='s'))
         for net in select_nets:

tests/test_passes.py

@@ -2,7 +2,6 @@
 import random
 import io
 import pyrtl
-from pyrtl import analysis
 from .test_inputoutput import full_adder_blif
 
 
@@ -60,7 +59,7 @@ def test_output_to_graphviz_does_not_throw_error(self):
     def test_output_to_graphviz_with_custom_namer_does_not_throw_error(self):
         with io.StringIO() as vfile:
             pyrtl.input_from_blif(full_adder_blif)
-            timing = analysis.TimingAnalysis()
+            timing = pyrtl.TimingAnalysis()
             node_fan_in = {net: len(net.args) for net in pyrtl.working_block()}
             graph_namer = pyrtl.graphviz_detailed_namer(
                 extra_node_info=node_fan_in,
@@ -70,15 +69,13 @@ def test_output_to_graphviz_with_custom_namer_does_not_throw_error(self):
 
     @unittest.skip("Need to make Graphviz output order deterministic via sorting")
     def test_output_to_graphviz_correct_detailed_output(self):
-        from pyrtl.analysis.estimate import TimingAnalysis
-
         a = pyrtl.Input(2, 'a')
         b = a * 8
         c = b[2:]
         d = pyrtl.Output(10, 'd')
         d <<= c
 
-        analysis = TimingAnalysis()
+        analysis = pyrtl.TimingAnalysis()
         _, dst_map = pyrtl.working_block().net_connections()
 
         def get_fanout(n):