We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
2 parents 1e9ad79 + 756d6c1 commit 20a2a2eCopy full SHA for 20a2a2e
tests/test_importexport.py
@@ -1650,7 +1650,7 @@ class TestVerilogInput(unittest.TestCase):
1650
def setUp(self):
1651
import subprocess
1652
try:
1653
- version = subprocess.check_output(['yosys', '--version'])
+ version = subprocess.check_output(['yosys', '-V'])
1654
except OSError:
1655
raise unittest.SkipTest('Testing Verilog input requires yosys')
1656
pyrtl.reset_working_block()
0 commit comments