Adding automatic reset for registers

Author: mdko

pyrtl/compilesim.py

@@ -86,14 +86,21 @@ def __init__(
         self._remove_untraceable()
 
         self.default_value = default_value
-        self._regmap, self._memmap = register_value_map, memory_value_map
+        self._regmap = {}  # Updated below
+        self._memmap = memory_value_map
         self._uid_counter = 0
         self.varname = {}  # mapping from wires and memories to C variables
 
+        for r in self.block.wirevector_subset(Register):
+            rval = register_value_map.get(r, r.reset_value)
+            if rval is None:
+                rval = self.default_value
+            self._regmap[r] = rval
+
         # Passing the dictionary objects themselves since they aren't updated anywhere.
         # If that's ever not the case, will need to pass in deep copies of them like done
         # for the normal Simulation so we retain the initial values that had.
-        self.tracer._set_initial_values(default_value, register_value_map, memory_value_map)
+        self.tracer._set_initial_values(default_value, self._regmap, self._memmap)
 
         self._create_dll()
         self._initialize_mems()
@@ -432,9 +439,11 @@ def _declare_wv(self, write, w):
             write('const uint64_t {name}[{limbs}] = {val};'.format(
                 limbs=self._limbs(w), name=vn, val=self._makeini(w, w.val)))
         elif isinstance(w, Register):
+            rval = self._regmap.get(w, w.reset_value)
+            if rval is None:
+                rval = self.default_value
             write('static uint64_t {name}[{limbs}] = {val};'.format(
-                limbs=self._limbs(w), name=vn,
-                val=self._makeini(w, self._regmap.get(w, self.default_value))))
+                limbs=self._limbs(w), name=vn, val=self._makeini(w, rval)))
         else:
             write('uint64_t {name}[{limbs}];'.format(limbs=self._limbs(w), name=vn))
 

pyrtl/importexport.py

@@ -157,7 +157,7 @@ def SLiteral(x):
     dffas_def = Group(SKeyword('.subckt') + dffas_keyword + dffas_formal)('dffas_def')
 
     # synchronous Flip-flop
-    dffs_init_val = Optional(oneOf("0 1 2 3"), default=Literal("0"))
+    dffs_init_val = Optional(oneOf('0 1 2 3'), default='0')
     # TODO I think <type> and <control> ('re' and 'C') below are technically optional too
     dffs_def = Group(SKeyword('.latch')
                      + signal_id('D')
@@ -345,19 +345,14 @@ def twire(w):
             ff_clk_set.add(command['C'])
 
         # Create register and assign next state to D and output to Q
+        # We ignore initialization values of 2 (don't care) and 3 (unknown).
         regname = command['Q'] + '_reg'
-        flop = Register(bitwidth=1)
+        init_val = command['I']
+        rval = {'0': 0, '1': 1, '2': None, '3': None}[init_val]
+        flop = Register(bitwidth=1, reset_value=rval)
         subckt.add_reg(regname, flop)
         flop.next <<= twire(command['D'])
         flop_output = twire(command['Q'])
-        init_val = command['I']
-        if init_val == "1":
-            # e.g. in Verilog: `initial reg <= 1;`
-            raise PyrtlError("Initializing latches to 1 is not supported. "
-                             "Acceptable values are: 0, 2 (don't care), and 3 (unknown); "
-                             "in any case, PyRTL will ensure all stateful elements come up 0. "
-                             "For finer control over the initial value, use specialized reset "
-                             "logic.")
         flop_output <<= flop
 
     def extract_model_reference(parent, command):
@@ -416,8 +411,22 @@ def instantiate(subckt):
 #
 
 
-def output_to_verilog(dest_file, block=None):
-    """ A function to walk the block and output it in verilog format to the open file. """
+def output_to_verilog(dest_file, add_reset=True, block=None):
+    """ A function to walk the block and output it in Verilog format to the open file.
+
+    :param dest_file: Open file where the Verilog output will be written
+    :param add_reset: If reset logic should be added. Allowable options are:
+        False (meaning no reset logic is added), True (default, for adding synchronous
+        reset logic), and 'asynchronous' (for adding asynchronous reset logic).
+    :param block: Block to be walked and exported
+
+    The registers will be set to their reset_value, if specified, otherwise 0.
+    """
+
+    if not isinstance(add_reset, bool):
+        if add_reset != 'asynchronous':
+            raise PyrtlError("Invalid add_reset option %s. Acceptable options are "
+                             "False, True, and 'asynchronous'")
 
     block = working_block(block)
     file = dest_file
@@ -429,15 +438,15 @@ def output_to_verilog(dest_file, block=None):
     def varname(wire):
         return internal_names[wire.name]
 
-    _to_verilog_header(file, block, varname)
+    _to_verilog_header(file, block, varname, add_reset)
     _to_verilog_combinational(file, block, varname)
-    _to_verilog_sequential(file, block, varname)
+    _to_verilog_sequential(file, block, varname, add_reset)
     _to_verilog_memories(file, block, varname)
     _to_verilog_footer(file)
 
 
 def OutputToVerilog(dest_file, block=None):
-    """ A deprecated function to output verilog, use "output_to_verilog" instead. """
+    """ A deprecated function to output Verilog, use "output_to_verilog" instead. """
     return output_to_verilog(dest_file, block)
 
 
@@ -487,7 +496,7 @@ def _verilog_block_parts(block):
     return inputs, outputs, registers, wires, memories
 
 
-def _to_verilog_header(file, block, varname):
+def _to_verilog_header(file, block, varname, add_reset):
     """ Print the header of the verilog implementation. """
 
     def name_sorted(wires):
@@ -504,13 +513,17 @@ def name_list(wires):
 
     # module name
     io_list = ['clk'] + name_list(name_sorted(inputs)) + name_list(name_sorted(outputs))
+    if add_reset:
+        io_list.insert(1, 'rst')
     if any(w.startswith('tmp') for w in io_list):
         raise PyrtlError('input or output with name starting with "tmp" indicates unnamed IO')
     io_list_str = ', '.join(io_list)
     print('module toplevel({:s});'.format(io_list_str), file=file)
 
     # inputs and outputs
     print('    input clk;', file=file)
+    if add_reset:
+        print('    input rst;', file=file)
     for w in name_sorted(inputs):
         print('    input{:s} {:s};'.format(_verilog_vector_decl(w), varname(w)), file=file)
     for w in name_sorted(outputs):
@@ -596,18 +609,33 @@ def name_sorted(wires):
     print('', file=file)
 
 
-def _to_verilog_sequential(file, block, varname):
+def _to_verilog_sequential(file, block, varname, add_reset):
     """ Print the sequential logic of the verilog implementation. """
     if not block.logic_subset(op='r'):
         return
 
     print('    // Registers', file=file)
-    print('    always @( posedge clk )', file=file)
+    if add_reset == 'asynchronous':
+        print('    always @(posedge clk or posedge rst)', file=file)
+    else:
+        print('    always @(posedge clk)', file=file)
     print('    begin', file=file)
+    if add_reset:
+        print('        if (rst) begin', file=file)
+        for net in _net_sorted(block.logic, varname):
+            if net.op == 'r':
+                dest = varname(net.dests[0])
+                rval = net.dests[0].reset_value
+                if rval is None:
+                    rval = 0
+                print('            {:s} <= {:d};'.format(dest, rval), file=file)
+        print('        end', file=file)
+    print('        else begin', file=file)
     for net in _net_sorted(block.logic, varname):
         if net.op == 'r':
             dest, src = (varname(net.dests[0]), varname(net.args[0]))
-            print('        {:s} <= {:s};'.format(dest, src), file=file)
+            print('            {:s} <= {:s};'.format(dest, src), file=file)
+    print('        end', file=file)
     print('    end', file=file)
     print('', file=file)
 
@@ -617,7 +645,7 @@ def _to_verilog_memories(file, block, varname):
     memories = {n.op_param[1] for n in block.logic_subset('m@')}
     for m in sorted(memories, key=lambda m: m.id):
         print('    // Memory mem_{}: {}'.format(m.id, m.name), file=file)
-        print('    always @( posedge clk )', file=file)
+        print('    always @(posedge clk)', file=file)
         print('    begin', file=file)
         for net in _net_sorted(block.logic_subset('@'), varname):
             if net.op_param[1] == m:
@@ -692,7 +720,16 @@ def name_list(wires):
 
     def init_regvalue(r):
         if simulation_trace:
-            return simulation_trace.init_regvalue.get(r, simulation_trace.default_value)
+            rval = simulation_trace.init_regvalue.get(r)
+            # Currently, the simulation stores the initial value for all registers
+            # in init_regvalue, so rval should not be None at this point.
+            # For the strange case where the trace was made by hand/other special use
+            # cases, check it against None anyway.
+            if rval is None:
+                rval = r.reset_value
+            if rval is None:
+                rval = simulation_trace.default_value
+            return rval
         else:
             return 0
 

pyrtl/simulation.py

@@ -52,7 +52,7 @@ class Simulation(object):
     }
 
     def __init__(
-            self, tracer=True, register_value_map=None, memory_value_map=None,
+            self, tracer=True, register_value_map={}, memory_value_map={},
             default_value=0, block=None):
         """ Creates a new circuit simulator.
 
@@ -61,14 +61,15 @@ def __init__(
             passed, no tracer is instantiated (which is good for long running simulations).
             If the default (true) is passed, Simulation will create a new tracer automatically
             which can be referenced by the member variable .tracer
-        :param register_value_map: Defines the initial value for
-            the registers specified. Format: {Register: value}.
+        :param register_value_map: Defines the initial value for the registers specified;
+            overrides the registers's reset_value. Format: {Register: value}.
         :param memory_value_map: Defines initial values for many
             addresses in a single or multiple memory. Format: {Memory: {address: Value}}.
             Memory is a memory block, address is the address of a value
-        :param default_value: is the value that all unspecified registers and
-            memories will initialize to. If no default_value is specified, it will
-            use the value stored in the object (default to 0)
+        :param default_value: The value that all unspecified registers and
+            memories will initialize to (default 0). For registers, this is the value that
+            will be used if the particular register doesn't have a specified reset_value,
+            and isn't found in the register_value_map.
         :param block: the hardware block to be traced (which might be of type PostSynthesisBlock).
             defaults to the working block
 
@@ -94,20 +95,23 @@ def __init__(
         self.tracer = tracer
         self._initialize(register_value_map, memory_value_map)
 
-    def _initialize(self, register_value_map=None, memory_value_map=None):
+    def _initialize(self, register_value_map={}, memory_value_map={}):
         """ Sets the wire, register, and memory values to default or as specified.
 
         :param register_value_map: is a map of {Register: value}.
         :param memory_value_map: is a map of maps {Memory: {address: Value}}.
-        :param default_value: is the value that all unspecified registers and memories will
-            default to. If no default_value is specified, it will use the value stored in the
-            object (default to 0)
+        :param default_value: is the value that all unspecified registers and
+            memories will initialize to (default 0). For registers, this is the value that
+            will be used if the particular register doesn't have a specified reset_value,
+            and isn't found in the register_value_map.
         """
         # set registers to their values
         reg_set = self.block.wirevector_subset(Register)
-        if register_value_map is not None:
-            for r in reg_set:
-                self.value[r] = self.regvalue[r] = register_value_map.get(r, self.default_value)
+        for r in reg_set:
+            rval = register_value_map.get(r, r.reset_value)
+            if rval is None:
+                rval = self.default_value
+            self.value[r] = self.regvalue[r] = rval
 
         # set constants to their set values
         for w in self.block.wirevector_subset(Const):
@@ -120,21 +124,20 @@ def _initialize(self, register_value_map=None, memory_value_map=None):
             if memid not in self.memvalue:
                 self.memvalue[memid] = {}
 
-        if memory_value_map is not None:
-            for (mem, mem_map) in memory_value_map.items():
-                if isinstance(mem, RomBlock):
-                    raise PyrtlError('error, one or more of the memories in the map is a RomBlock')
-                if isinstance(self.block, PostSynthBlock):
-                    mem = self.block.mem_map[mem]  # pylint: disable=maybe-no-member
-                self.memvalue[mem.id] = mem_map
-                max_addr_val, max_bit_val = 2**mem.addrwidth, 2**mem.bitwidth
-                for (addr, val) in mem_map.items():
-                    if addr < 0 or addr >= max_addr_val:
-                        raise PyrtlError('error, address %s in %s outside of bounds' %
-                                         (str(addr), mem.name))
-                    if val < 0 or val >= max_bit_val:
-                        raise PyrtlError('error, %s at %s in %s outside of bounds' %
-                                         (str(val), str(addr), mem.name))
+        for (mem, mem_map) in memory_value_map.items():
+            if isinstance(mem, RomBlock):
+                raise PyrtlError('error, one or more of the memories in the map is a RomBlock')
+            if isinstance(self.block, PostSynthBlock):
+                mem = self.block.mem_map[mem]  # pylint: disable=maybe-no-member
+            self.memvalue[mem.id] = mem_map
+            max_addr_val, max_bit_val = 2**mem.addrwidth, 2**mem.bitwidth
+            for (addr, val) in mem_map.items():
+                if addr < 0 or addr >= max_addr_val:
+                    raise PyrtlError('error, address %s in %s outside of bounds' %
+                                     (str(addr), mem.name))
+                if val < 0 or val >= max_bit_val:
+                    raise PyrtlError('error, %s at %s in %s outside of bounds' %
+                                     (str(val), str(addr), mem.name))
 
         # set all other variables to default value
         for w in self.block.wirevector_set:
@@ -437,7 +440,7 @@ class FastSimulation(object):
     #  when put into the generated code
 
     def __init__(
-            self, register_value_map=None, memory_value_map=None,
+            self, register_value_map={}, memory_value_map={},
             default_value=0, tracer=True, block=None, code_file=None):
         """ Instantiates a Fast Simulation instance.
 
@@ -469,17 +472,17 @@ def __init__(
         self.internal_names = _PythonSanitizer('_fastsim_tmp_')
         self._initialize(register_value_map, memory_value_map)
 
-    def _initialize(self, register_value_map=None, memory_value_map=None):
-        if register_value_map is None:
-            register_value_map = {}
-
+    def _initialize(self, register_value_map={}, memory_value_map={}):
         for wire in self.block.wirevector_set:
             self.internal_names.make_valid_string(wire.name)
 
         # set registers to their values
         reg_set = self.block.wirevector_subset(Register)
         for r in reg_set:
-            self.regs[r.name] = register_value_map.get(r, self.default_value)
+            rval = register_value_map.get(r, r.reset_value)
+            if rval is None:
+                rval = self.default_value
+            self.regs[r.name] = rval
 
         self._initialize_mems(memory_value_map)
 
@@ -497,12 +500,11 @@ def _initialize(self, register_value_map=None, memory_value_map=None):
         self.sim_func = context['sim_func']
 
     def _initialize_mems(self, memory_value_map):
-        if memory_value_map is not None:
-            for (mem, mem_map) in memory_value_map.items():
-                if isinstance(mem, RomBlock):
-                    raise PyrtlError('error, one or more of the memories in the map is a RomBlock')
-                name = self._mem_varname(mem)
-                self.mems[name] = mem_map
+        for (mem, mem_map) in memory_value_map.items():
+            if isinstance(mem, RomBlock):
+                raise PyrtlError('error, one or more of the memories in the map is a RomBlock')
+            name = self._mem_varname(mem)
+            self.mems[name] = mem_map
 
         for net in self.block.logic_subset('m@'):
             mem = net.op_param[1]
@@ -1227,7 +1229,7 @@ def _set_initial_values(self, default_value, init_regvalue, init_memvalue):
 
         :param default_value: Default value to be used for all registers and
             memory locations if not found in the other passed in maps
-        :param init_regvalue: Default value for registers
+        :param init_regvalue: Default value for all the registers
         :param init_memvvalue: Default value for memory locations of given maps
 
         This is needed when using this trace for outputting a Verilog testbench,

pyrtl/wire.py

@@ -706,9 +706,33 @@ def __init__(self, rhs, is_conditional):
             self.rhs = rhs
             self.is_conditional = is_conditional
 
-    def __init__(self, bitwidth, name='', block=None):
+    def __init__(self, bitwidth, name='', reset_value=None, block=None):
+        """ Construct a register.
+
+        :param int bitwidth: Number of bits to represent this register.
+        :param String name: The name of the wire.  Must be unique. If none
+            is provided, one will be autogenerated.
+        :param reset_value: Value to initialize this register to during simulation
+            and in any code (e.g. Verilog) that is exported. Defaults to 0, but can
+            be explicitly overridden at simulation time.
+        :param block: The block under which the wire should be placed.
+            Defaults to the working block.
+        :return: a WireVector object representing a register.
+
+        It is an error if the reset_value cannot fit into the specified bitwidth
+        for this register.
+        """
+        from pyrtl.helperfuncs import infer_val_and_bitwidth
+
         super(Register, self).__init__(bitwidth=bitwidth, name=name, block=block)
         self.reg_in = None  # wire vector setting self.next
+        if reset_value is not None:
+            reset_value, rst_bitwidth = infer_val_and_bitwidth(reset_value)
+            if rst_bitwidth > bitwidth:
+                raise PyrtlError(
+                    'reset_value "%s" cannot fit in the specified %d bits for this register'
+                    % (str(reset_value), bitwidth))
+        self.reset_value = reset_value
 
     @property
     def next(self):