Merge branch 'development' of https://github.com/UCSBarchlab/PyRTL into development

Author: timsherwood

pyrtl/inputoutput.py

@@ -58,11 +58,15 @@ def twire(x):
         s = block.get_wirevector_by_name(x)
         if s is None:
             s = WireVector(bitwidth=1, name=x)
-        if isinstance(s, Output) and (merge_io_vectors or len(x) == 1):
+        elif isinstance(s, Output):
             # To allow an output wire to be used as an argument (legal in BLIF),
-            # use the intermediate wire that was created in its place. extract_outputs()
-            # creates this intermediate wire.
-            s = block.get_wirevector_by_name(x + '[0]')
+            # use the intermediate wire that was created in its place.
+            # extract_outputs() creates this intermediate wire. Must check for
+            # merge_io_vectors first!
+            if not merge_io_vectors:
+                s = block.get_wirevector_by_name(x + '_i')
+            elif len(s) == 1:
+                s = block.get_wirevector_by_name(x + '[0]')
         return s
 
     # Begin BLIF language definition
@@ -117,35 +121,49 @@ def extract_inputs(model):
             bitwidth = name_counts[input_name]
             if input_name == clock_name:
                 clk_set.add(input_name)
-            elif not merge_io_vectors or bitwidth == 1:
-                block.add_wirevector(Input(bitwidth=1, name=input_name))
-            else:
+            elif bitwidth == 1:
+                block.add_wirevector(Input(bitwidth=1, name=input_name, block=block))
+            elif merge_io_vectors:
                 wire_in = Input(bitwidth=bitwidth, name=input_name, block=block)
                 for i in range(bitwidth):
                     bit_name = input_name + '[' + str(i) + ']'
                     bit_wire = WireVector(bitwidth=1, name=bit_name, block=block)
                     bit_wire <<= wire_in[i]
+            else:
+                for i in range(bitwidth):
+                    bit_name = input_name + '[' + str(i) + ']'
+                    block.add_wirevector(Input(bitwidth=1, name=bit_name, block=block))
 
     def extract_outputs(model):
         start_names = [re.sub(r'\[([0-9]+)\]$', '', x) for x in model['output_list']]
         name_counts = collections.Counter(start_names)
         for output_name in name_counts:
             bitwidth = name_counts[output_name]
-            if not merge_io_vectors or bitwidth == 1:
-                # To allow an output wire to be used as an argument (legal in BLIF),
-                # create an intermediate wire that will be used in its place. twire()
-                # checks for this and uses the intermediate wire when needed
-                w = WireVector(bitwidth=1, name=output_name + '[0]')
-                out = Output(bitwidth=1, name=output_name)
-                out <<= w
-            else:
+            # To allow an output wire to be used as an argument (legal in BLIF),
+            # we need to create an intermediate wire, which will be used in twire()
+            # whenever the original wire is referenced. For example, given 2-bit Output 'a',
+            # every access to 'a[1]' will really be a reference to 'a[1]_i', a normal
+            # WireVector connected to 'a[1]'. A key property is that the name by
+            # which all other parts of the code refer to this wire doesn't change;
+            # the only thing that changes is what underlying wire is used.
+            if bitwidth == 1:
+                bit_internal = WireVector(bitwidth=1, name=output_name + '[0]', block=block)
+                bit_out = Output(bitwidth=1, name=output_name, block=block)
+                bit_out <<= bit_internal
+            elif merge_io_vectors:
                 wire_out = Output(bitwidth=bitwidth, name=output_name, block=block)
                 bit_list = []
                 for i in range(bitwidth):
                     bit_name = output_name + '[' + str(i) + ']'
                     bit_wire = WireVector(bitwidth=1, name=bit_name, block=block)
                     bit_list.append(bit_wire)
                 wire_out <<= concat_list(bit_list)
+            else:
+                for i in range(bitwidth):
+                    bit_name = output_name + '[' + str(i) + ']'
+                    bit_internal = WireVector(bitwidth=1, name=bit_name + '_i', block=block)
+                    bit_out = Output(bitwidth=1, name=bit_name, block=block)
+                    bit_out <<= bit_internal
 
     def extract_commands(model):
         # for each "command" (dff or net) in the model

tests/test_inputoutput.py

@@ -238,6 +238,23 @@
 .end
 """  # noqa
 
+simple_unmerged_io_blif = """
+# Generated by Yosys 0.9+2406 (git sha1 aee43936, clang 11.0.3 -fPIC -Os)
+
+.model top
+.inputs a[0] a[1] a[2] a[3]
+.outputs b[0] b[1]
+.names $false
+.names $true
+1
+.names $undef
+.names a[0] b[0]
+1 1
+.names a[2] b[1]
+1 1
+.end
+"""  # noqa
+
 
 class TestInputFromBlif(unittest.TestCase):
     def setUp(self):
@@ -304,6 +321,21 @@ def test_sequential_blif_input_has_correct_io_interface_counter(self):
         io_output = pyrtl.working_block().wirevector_subset(pyrtl.Output)
         self.assertIn(count, io_output)
 
+    def test_correct_interface_with_unmerged_io(self):
+        pyrtl.input_from_blif(simple_unmerged_io_blif, merge_io_vectors=False)
+        a0, a1, a2, a3, b0, b1 = [
+            pyrtl.working_block().get_wirevector_by_name(s)
+            for s in ['a[0]', 'a[1]', 'a[2]', 'a[3]', 'b[0]', 'b[1]']
+        ]
+        self.assertEquals(len(a0), 1)
+        self.assertEquals(len(a1), 1)
+        self.assertEquals(len(a2), 1)
+        self.assertEquals(len(a3), 1)
+        self.assertEquals(len(b0), 1)
+        self.assertEquals(len(b1), 1)
+        self.assertEquals({a0, a1, a2, a3}, pyrtl.working_block().wirevector_subset(pyrtl.Input))
+        self.assertEquals({b0, b1}, pyrtl.working_block().wirevector_subset(pyrtl.Output))
+
     def test_blif_input_simulates_correctly_with_merged_outputs(self):
         # The 'counter_blif' string contains a model of a standard 4-bit synchronous-reset
         # counter with enable. In particular, the model has 4 1-bit outputs named "count[0]",
@@ -332,6 +364,44 @@ def test_blif_input_simulates_correctly_with_merged_outputs(self):
         sim_trace.print_trace(output)
         self.assertEqual(output.getvalue(), correct_output)
 
+    def test_blif_input_simulates_correctly_with_unmerged_outputs(self):
+        pyrtl.input_from_blif(counter4bit_blif, merge_io_vectors=False)
+        count0, count1, count2, count3 = [
+            pyrtl.working_block().get_wirevector_by_name(s)
+            for s in ['count[0]', 'count[1]', 'count[2]', 'count[3]']
+        ]
+        self.assertEquals(len(count0), 1)
+        self.assertEquals(len(count1), 1)
+        self.assertEquals(len(count2), 1)
+        self.assertEquals(len(count3), 1)
+        io_vectors = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
+        sim_trace = pyrtl.SimulationTrace(wires_to_track=io_vectors)
+        sim = pyrtl.Simulation(sim_trace)
+        inputs = {
+            'rst': [1] + [0] * 20,
+            'en': [1] + [1] * 20,
+        }
+        expected_merged = [0] + list(range(0, 16)) + list(range(0, 4))
+
+        expected = {
+            'count[0]': [n & 0b0001 for n in expected_merged],
+            'count[1]': [(n & 0b0010) >> 1 for n in expected_merged],
+            'count[2]': [(n & 0b0100) >> 2 for n in expected_merged],
+            'count[3]': [(n & 0b1000) >> 3 for n in expected_merged],
+        }
+        sim.step_multiple(inputs, expected)
+
+        correct_output = ("     --- Values in base 10 ---\n"
+                          "count[0] 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1\n"
+                          "count[1] 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1\n"
+                          "count[2] 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0\n"
+                          "count[3] 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0\n"
+                          "en       1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1\n"
+                          "rst      1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n")
+        output = six.StringIO()
+        sim_trace.print_trace(output)
+        self.assertEqual(output.getvalue(), correct_output)
+
     def test_sequential_blif_input_fails_to_parse_with_bad_latch_init(self):
         with self.assertRaises(pyrtl.PyrtlError):
             pyrtl.input_from_blif(counter4bit_blif_bad_latch_inits)