Add optimization pass that removes unneeded slices

Author: mdko

pyrtl/passes.py

@@ -46,6 +46,7 @@ def optimize(update_working_block=True, block=None, skip_sanity_check=False):
         if (not skip_sanity_check) or _get_debug_mode():
             block.sanity_check()
         _remove_wire_nets(block)
+        _remove_slice_nets(block)
         constant_propagation(block, True)
         _remove_unlistened_nets(block)
         common_subexp_elimination(block)
@@ -103,6 +104,67 @@ def _remove_wire_nets(block):
     block.sanity_check()
 
 
+def _remove_slice_nets(block):
+    """ Remove all unneeded slice nodes from the block.
+
+    Unneeded here means that the source and destination wires of a slice net are exactly
+    the same, because the slice takes all the bits, in order, from the source.
+    """
+    # Turns a net of form on the left into the one on the right:
+    #
+    #  w1
+    #   |
+    # [3:0]
+    #   |
+    # [3:0]     ===>  w1
+    #   |             |
+    # [3:0] w2      [3:0] w2
+    #  / \ /         / \ /
+    # ~   +         ~   +
+    # |   |         |   |
+
+    wire_src_dict = _ProducerList()
+    wire_removal_set = set()  # set of all wirevectors to be removed
+
+    def is_net_slicing_entire_wire(net):
+        if net.op != 's':
+            return False
+
+        src_wire = net.args[0]
+        dst_wire = net.dests[0]
+        if len(src_wire) != len(dst_wire):
+            return False
+
+        selLower = net.op_param[0]
+        selUpper = net.op_param[-1]
+        # Check if getting all bits from the src_wire (i.e. consecutive bits, MSB to LSB)
+        return net.op_param == tuple(range(selLower, selUpper + 1))
+
+    # one pass to build the map of value producers and
+    # all of the nets and wires to be removed
+    for net in block.logic:
+        if is_net_slicing_entire_wire(net):
+            wire_src_dict[net.dests[0]] = net.args[0]
+            if not isinstance(net.dests[0], Output):
+                wire_removal_set.add(net.dests[0])
+
+    # second full pass to create the new logic without the wire nets
+    new_logic = set()
+    for net in block.logic:
+        if not is_net_slicing_entire_wire(net) or isinstance(net.dests[0], Output):
+            new_args = tuple(wire_src_dict.find_producer(x) for x in net.args)
+            new_net = LogicNet(net.op, net.op_param, new_args, net.dests)
+            new_logic.add(new_net)
+
+    # now update the block with the new logic and remove wirevectors
+    block.logic = new_logic
+    for dead_wirevector in wire_removal_set:
+        del block.wirevector_by_name[dead_wirevector.name]
+        block.wirevector_set.remove(dead_wirevector)
+
+    block.sanity_check()
+
+
 def constant_propagation(block, silence_unexpected_net_warnings=False):
     """ Removes excess constants in the block.
 

tests/test_passes.py

@@ -253,7 +253,6 @@ def test_wire_net_removal_1(self):
         outwire = pyrtl.Output()
         tempwire <<= inwire
         outwire <<= tempwire
-
         pyrtl.synthesize()
         pyrtl.optimize()
         block = pyrtl.working_block()
@@ -276,6 +275,49 @@ def test_wire_net_removal_2(self):
         self.assert_num_net(5, block)
         self.assert_num_wires(6, block)
 
+    def test_slice_net_removal_1(self):
+        constwire = pyrtl.Const(1, 1)
+        inwire = pyrtl.Input(bitwidth=1)
+        outwire = pyrtl.Output()
+        outwire <<= constwire ^ inwire
+        pyrtl.optimize()
+        block = pyrtl.working_block()
+        self.num_net_of_type('s', 0, block)
+        self.num_net_of_type('~', 1, block)
+
+    def test_slice_net_removal_2(self):
+        inwire = pyrtl.Input(bitwidth=3)
+        outwire = pyrtl.Output()
+        tempwire = inwire[0:3]
+        outwire <<= tempwire[0:3]
+        pyrtl.optimize()
+        block = pyrtl.working_block()
+        self.num_net_of_type('s', 0, block)
+        self.num_net_of_type('w', 1, block)
+
+    def test_slice_net_removal_3(self):
+        inwire = pyrtl.Input(bitwidth=3)
+        outwire = pyrtl.Output()
+        tempwire = inwire[0:2]
+        outwire <<= tempwire[0:2]
+        pyrtl.optimize()
+        # Removes one of the slices, which does nothing.
+        block = pyrtl.working_block()
+        self.num_net_of_type('s', 1, block)
+        self.num_net_of_type('w', 1, block)
+
+    def test_slice_net_removal_4(self):
+        inwire = pyrtl.Input(bitwidth=4)
+        outwire1 = pyrtl.Output()
+        outwire2 = pyrtl.Output()
+        outwire1 <<= inwire[0:4]
+        outwire2 <<= inwire[0:3]
+        pyrtl.optimize()
+        # Removes just the outwire1 slice, which does nothing.
+        block = pyrtl.working_block()
+        self.num_net_of_type('s', 1, block)
+        self.num_net_of_type('w', 2, block)
+
 
 class TestConstFolding(NetWireNumTestCases):
     def setUp(self):
@@ -343,8 +385,8 @@ def test_adv_one_var_op_2(self):
         # Note: the current implementation still sticks a wire net between
         # a register 'nextsetter' wire and the output wire
         self.num_net_of_type('w', 1, block)
-        self.assert_num_net(4, block)
-        self.assert_num_wires(5, block)
+        self.assert_num_net(3, block)
+        self.assert_num_wires(4, block)
         self.num_wire_of_type(Const, 0, block)
         self.num_wire_of_type(Output, 1, block)
 
@@ -412,9 +454,9 @@ def test_two_var_op_produce_not(self):
         block = pyrtl.working_block(None)
         self.num_net_of_type('~', 1, block)
         self.num_net_of_type('w', 1, block)
-        self.num_net_of_type('s', 1, block)  # due to synthesis
-        self.assert_num_net(3, block)
-        self.assert_num_wires(4, block)
+        self.num_net_of_type('s', 0, block)
+        self.assert_num_net(2, block)
+        self.assert_num_wires(3, block)
         self.num_wire_of_type(Const, 0, block)
 
     def test_two_var_op_correct_wire_prop(self):
@@ -703,7 +745,7 @@ def test_wirevector_1(self):
         outwire <<= ~tempwire2
         self.everything_t_procedure(48.5, 48.5)
         block = pyrtl.working_block()
-        self.assert_num_net(3, block)
+        self.assert_num_net(2, block)
 
     def test_combo_1(self):
         inwire, inwire2 = pyrtl.Input(bitwidth=1), pyrtl.Input(bitwidth=1)