Allow negative Register reset values#464

Merged

fdxmw merged 7 commits intoUCSBarchlab:developmentfrom

PrajwalVandana:patch-1

Feb 27, 2025

Commits on Feb 19, 2025

Allow negative Register reset values
PrajwalVandana
authored

Commits on Feb 23, 2025

allow negative reset values to Register, add/edit tests for this behavior
PrajwalVandana
committed

Commits on Feb 24, 2025

Merge branch 'development' into patch-1
PrajwalVandana
authored

Commits on Feb 26, 2025

sign extend negative Verilog string Register reset values, generalize tests
PrajwalVandana
committed
move Register reset value sign extension logic to helperfuncs._convert_verilog_str
PrajwalVandana
committed

Commits on Feb 27, 2025