👋 Hi there!
We are a team of Electrical and Electronic Engineers studying at the University of Technology Sydney (UTS).
Our focus lies in FPGA design, digital logic, and embedded systems — transforming HDL into hardware and ideas into innovation.
- 🔧 FPGA Design & Verification — VHDL/Verilog development, simulation, synthesis, and timing analysis
- 🌐 Networking & Protocols — Custom 10BASE-T switch design, Manchester encoding, CRC-32 modules, and PHY interfacing
- ⚙️ Embedded Systems — MCU integration, bus communication, and control logic
- 📈 Testing & Validation — Automated testbenches, functional verification, and post-synthesis debugging
| 🧱 Project | 💡 Description | 🧰 Technologies |
|---|---|---|
| Cyclone IV Ethernet Switch | FPGA-based 10BASE-T switch featuring custom CRC, Manchester encoder/decoder, and buffer controller | VHDL · Quartus Prime · ModelSim |
We’re a small, hands-on team of engineers who enjoy the craft of digital design — from HDL synthesis and PCB routing to testing on real silicon.
We thrive on collaboration, problem-solving, and a touch of over-engineering elegance.
🧠 “Measure twice, simulate once, synthesise forever.”
- 🎨 Profile Artwork: PFP designed by Freepik
- 🎓 University: University of Technology Sydney (UTS)
- 🛠️ Core Domains: FPGA · Digital Systems · Embedded Electronics · Engineering Innovation
📫 Got questions, ideas, or collaboration requests?
Start a Discussion or open an Issue in our repositories — we love talking HDL design, verification strategy, and hardware experimentation.
⭐ Star our projects if you find them useful or interesting!
