Feature/wishbone

Wishbone/vB3/Wishbone.vhdl

@@ -0,0 +1,124 @@
+-- =============================================================================
+-- Authors:
+--   Parham Soltani
+--
+-- Package:
+--   VHDL-2019 Wishbone interface descriptions
+--
+-- Description:
+--   Signal names use full descriptive UpperCamelCase names for clarity
+--
+-- License:
+-- =============================================================================
+-- Copyright 2025-2025 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+use     work.WishboneCommon.all;
+
+package Wishbone is
+	-- Tag Interface for optional tag signals
+	type Wishbone_Tag_Interface is record
+		Cycle   : Tag_Cycle_Type;
+		Address : Tag_Address_Type;
+		DataOut : Tag_Data_Type;
+		DataIn  : Tag_Data_Type;
+	end record;
+
+	-- Full Wishbone Interface (using descriptive full names)
+	type Wishbone_Interface is record
+		-- Master signals (outputs from master perspective)
+		Cycle       : std_ulogic;     -- CYC_O - Cycle
+		Strobe      : std_ulogic;     -- STB_O - Strobe
+		WriteEnable : std_ulogic;     -- WE_O  - Write Enable
+		Address     : Address_Type;   -- ADR_O - Address
+		DataOut     : Data_Type;      -- DAT_O - Data (Master to Slave)
+		Select      : Select_Type;    -- SEL_O - Select
+
+		-- Slave signals (outputs from slave perspective)
+		Acknowledge : std_ulogic;     -- ACK_I - Acknowledge
+		Error       : std_ulogic;     -- ERR_I - Error
+		Retry       : std_ulogic;     -- RTY_I - Retry
+		DataIn      : Data_Type;      -- DAT_I - Data (Slave to Master)
+
+		-- Optional signals for pipelined/burst modes
+		CycleType   : CycleType_Type; -- CTI_O - Cycle Type Identifier
+		BurstType   : BurstType_Type; -- BTE_O - Burst Type Extension
+
+		-- Optional signals
+		Tag         : Wishbone_Tag_Interface;
+		Lock        : std_ulogic;     -- LOCK_O - Lock
+		Stall       : std_ulogic;     -- STALL_I - Pipeline stall
+	end record;
+	type Wishbone_Interface_Vector is array(natural range <>) of Wishbone_Interface;
+
+	-- Master view (from master's perspective)
+	view Wishbone_MasterView of Wishbone_Interface is
+		-- Master outputs
+		Cycle       : out;
+		Strobe      : out;
+		WriteEnable : out;
+		Address     : out;
+		DataOut     : out;
+		Select      : out;
+		CycleType   : out;
+		BurstType   : out;
+		Tag         : out;
+		Lock        : out;
+
+		-- Master inputs (slave outputs)
+		Acknowledge : in;
+		Error       : in;
+		Retry       : in;
+		DataIn      : in;
+		Stall       : in;
+	end view;
+	alias Wishbone_SlaveView is Wishbone_MasterView'converse;
+
+	-- Simplified interface without optional signals
+	type Wishbone_Simple_Interface is record
+		-- Master signals
+		Cycle       : std_ulogic;
+		Strobe      : std_ulogic;
+		WriteEnable : std_ulogic;
+		Address     : Address_Type;
+		DataOut     : Data_Type;
+		Select      : Select_Type;
+
+		-- Slave signals
+		Acknowledge : std_ulogic;
+		DataIn      : Data_Type;
+	end record;
+	type Wishbone_Simple_Interface_Vector is array(natural range <>) of Wishbone_Simple_Interface;
+
+	view Wishbone_Simple_MasterView of Wishbone_Simple_Interface is
+		-- Master outputs
+		Cycle       : out;
+		Strobe      : out;
+		WriteEnable : out;
+		Address     : out;
+		DataOut     : out;
+		Select      : out;
+
+		-- Master inputs
+		Acknowledge : in;
+		DataIn      : in;
+	end view;
+	alias Wishbone_Simple_SlaveView is Wishbone_Simple_MasterView'converse;
+
+end package;

Wishbone/vB3/WishboneCommon.vhdl

@@ -0,0 +1,61 @@
+-- =============================================================================
+-- Authors:
+--   Parham Soltani
+--
+-- Package:
+--   Common types for Wishbone interfaces
+--
+-- Description:
+--   Defines shared types like Address_Type, Data_Type for use in Wishbone 
+--   records, following the Wishbone B.4 specification.
+--
+-- License:
+-- =============================================================================
+-- Copyright 2025-2025 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+library IEEE;
+use     IEEE.std_logic_1164.all;
+use     IEEE.numeric_std.all;
+
+package WishboneCommon is
+	-- Common types
+	subtype Data_Type        is std_ulogic_vector;
+	subtype Address_Type     is unsigned;
+	subtype Select_Type      is std_ulogic_vector;
+	subtype Tag_Cycle_Type   is std_ulogic_vector;
+	subtype Tag_Address_Type is std_ulogic_vector;
+	subtype Tag_Data_Type    is std_ulogic_vector;
+
+	-- Cycle Type Identifiers (CTI)
+	subtype CycleType_Type is std_ulogic_vector(2 downto 0);
+	constant WB_CTI_CLASSIC        : CycleType_Type := "000";  -- Classic cycle
+	constant WB_CTI_CONST_BURST    : CycleType_Type := "001";  -- Constant address burst
+	constant WB_CTI_INCR_BURST     : CycleType_Type := "010";  -- Incrementing burst
+	constant WB_CTI_END_OF_BURST   : CycleType_Type := "111";  -- End of burst
+
+	-- Burst Type Extension (BTE)
+	subtype BurstType_Type is std_ulogic_vector(1 downto 0);
+	constant WB_BTE_LINEAR         : BurstType_Type := "00";   -- Linear burst
+	constant WB_BTE_WRAP_4         : BurstType_Type := "01";   -- 4-beat wrap burst
+	constant WB_BTE_WRAP_8         : BurstType_Type := "10";   -- 8-beat wrap burst
+	constant WB_BTE_WRAP_16        : BurstType_Type := "11";   -- 16-beat wrap burst
+
+	type Wishbone_System_Interface is record
+		Clock    : std_ulogic;
+		Reset    : std_ulogic;
+	end record;
+
+end package;

Wishbone/vB3/Wishbone_Generic.vhdl

@@ -0,0 +1,79 @@
+-- =============================================================================
+-- Authors:
+--   Parham Soltani
+--
+-- Package:
+--   Generic Wishbone interface for pre-constraining widths
+--
+-- Description:
+--   Uses full UpperCamelCase names matching the Wishbone interface records
+--
+-- License:
+-- =============================================================================
+-- Copyright 2025-2025 Open Source VHDL Group
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--    http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- =============================================================================
+
+use work.Wishbone.all;
+
+package Wishbone_Generic is
+	generic (
+		constant ADDRESS_BITS : positive;
+		constant DATA_BITS    : positive;
+		constant TGD_BITS     : positive := 1;
+		constant TGA_BITS     : positive := 1;
+		constant TGC_BITS     : positive := 1
+	);
+
+	constant SEL_BITS : positive := DATA_BITS / 8;
+
+	-- Full Wishbone interface with all optional signals
+	subtype Wishbone_SizedInterface is Wishbone_Interface(
+		Address(ADDRESS_BITS - 1 downto 0),
+		DataOut(DATA_BITS - 1 downto 0),
+		DataIn(DATA_BITS - 1 downto 0),
+		Select(SEL_BITS - 1 downto 0),
+		Tag.DataOut(TGD_BITS - 1 downto 0),
+		Tag.DataIn(TGD_BITS - 1 downto 0),
+		Tag.Address(TGA_BITS - 1 downto 0),
+		Tag.Cycle(TGC_BITS - 1 downto 0)
+	);
+
+	subtype Wishbone_SizedInterface_Vector is Wishbone_Interface_Vector(open)(
+		Address(ADDRESS_BITS - 1 downto 0),
+		DataOut(DATA_BITS - 1 downto 0),
+		DataIn(DATA_BITS - 1 downto 0),
+		Select(SEL_BITS - 1 downto 0),
+		Tag.DataOut(TGD_BITS - 1 downto 0),
+		Tag.DataIn(TGD_BITS - 1 downto 0),
+		Tag.Address(TGA_BITS - 1 downto 0),
+		Tag.Cycle(TGC_BITS - 1 downto 0)
+	);
+
+	-- Simplified Wishbone interface
+	subtype Wishbone_Simple_SizedInterface is Wishbone_Simple_Interface(
+		Address(ADDRESS_BITS - 1 downto 0),
+		DataOut(DATA_BITS - 1 downto 0),
+		DataIn(DATA_BITS - 1 downto 0),
+		Select(SEL_BITS - 1 downto 0)
+	);
+
+	subtype Wishbone_Simple_SizedInterface_Vector is Wishbone_Simple_Interface_Vector(open)(
+		Address(ADDRESS_BITS - 1 downto 0),
+		DataOut(DATA_BITS - 1 downto 0),
+		DataIn(DATA_BITS - 1 downto 0),
+		Select(SEL_BITS - 1 downto 0)
+	);
+
+end package;

build.pro

@@ -33,6 +33,22 @@ analyze AMBA/AXI/v4/AXI4Lite.presized.vhdl
 analyze AMBA/AXI/v4/AXI4Stream.vhdl
 analyze AMBA/AXI/v4/AXI4Stream_Generic.vhdl
 
+# Avalon interfaces
+analyze Avalon/v1/AvalonCommon.vhdl
+analyze Avalon/v1/AvalonMM.vhdl
+analyze Avalon/v1/AvalonMM_Generic.vhdl
+analyze Avalon/v1/AvalonMM_Minimal.vhdl
+analyze Avalon/v1/AvalonMM_Minimal_Generic.vhdl
+analyze Avalon/v1/AvalonST.vhdl
+analyze Avalon/v1/AvalonST_Generic.vhdl
+analyze Avalon/v1/AvalonST_Minimal.vhdl
+analyze Avalon/v1/AvalonST_Minimal_Generic.vhdl
+
+# Wishbone interfaces
+analyze Wishbone/vB3/WishboneCommon.vhdl
+analyze Wishbone/vB3/Wishbone.vhdl
+analyze Wishbone/vB3/Wishbone_Generic.vhdl
+
 # Low-speed interfaces
 analyze IO/I2C.vhdl
 analyze IO/SPI.vhdl
@@ -52,14 +68,3 @@ analyze MIPI/M-PHY.vhdl
 
 # Miscellaneous interfaces
 analyze PoC/CSE.vhdl
-
-# Avalon interfaces
-analyze Avalon/v1/AvalonCommon.vhdl
-analyze Avalon/v1/AvalonMM.vhdl
-analyze Avalon/v1/AvalonMM_Generic.vhdl
-analyze Avalon/v1/AvalonMM_Minimal.vhdl
-analyze Avalon/v1/AvalonMM_Minimal_Generic.vhdl
-analyze Avalon/v1/AvalonST.vhdl
-analyze Avalon/v1/AvalonST_Generic.vhdl
-analyze Avalon/v1/AvalonST_Minimal.vhdl
-analyze Avalon/v1/AvalonST_Minimal_Generic.vhdl

compileorder.list

@@ -31,6 +31,22 @@ AMBA/AXI/v4/AXI4Lite.presized.vhdl
 AMBA/AXI/v4/AXI4Stream.vhdl
 AMBA/AXI/v4/AXI4Stream_Generic.vhdl
 
+# Avalon Memory-Mapped Interfaces
+Avalon/v1/AvalonCommon.vhdl
+Avalon/v1/AvalonMM.vhdl
+Avalon/v1/AvalonMM_Generic.vhdl
+Avalon/v1/AvalonMM_Minimal.vhdl
+Avalon/v1/AvalonMM_Minimal_Generic.vhdl
+Avalon/v1/AvalonST.vhdl
+Avalon/v1/AvalonST_Generic.vhdl
+Avalon/v1/AvalonST_Minimal.vhdl
+Avalon/v1/AvalonST_Minimal_Generic.vhdl
+
+# Wishbone B.3 Interfaces  
+Wishbone/vB3/WishboneCommon.vhdl
+Wishbone/vB3/Wishbone.vhdl
+Wishbone/vB3/Wishbone_Generic.vhdl
+
 # Low-speed interfaces
 IO/I2C.vhdl
 IO/SPI.vhdl
@@ -50,14 +66,3 @@ MIPI/M-PHY.vhdl
 
 # Miscellaneous interfaces
 PoC/CSE.vhdl
-
-# Avalon Memory-Mapped Interfaces
-Avalon/v1/AvalonCommon.vhdl
-Avalon/v1/AvalonMM.vhdl
-Avalon/v1/AvalonMM_Generic.vhdl
-Avalon/v1/AvalonMM_Minimal.vhdl
-Avalon/v1/AvalonMM_Minimal_Generic.vhdl
-Avalon/v1/AvalonST.vhdl
-Avalon/v1/AvalonST_Generic.vhdl
-Avalon/v1/AvalonST_Minimal.vhdl
-Avalon/v1/AvalonST_Minimal_Generic.vhdl