Update clock periods in SDC files for aes, gcd, and riscv32i

leeway64 · leeway64 · commit c8b4b2a3a330 · 2025-10-26T16:41:13.000-07:00
diff --git a/flow/designs/sky130hd/aes/two_phase_clk_constraint.sdc b/flow/designs/sky130hd/aes/two_phase_clk_constraint.sdc
@@ -3,7 +3,7 @@
 current_design aes_cipher_top
 
 
-set clk_period 3.46
+set clk_period 3.47
 set clk_io_pct 0.2
 set duty_cycle 0.49
 
diff --git a/flow/designs/sky130hd/gcd/two_phase_clk_constraint.sdc b/flow/designs/sky130hd/gcd/two_phase_clk_constraint.sdc
@@ -2,7 +2,7 @@
 
 current_design gcd
 
-set clk_period 3.41
+set clk_period 3.99
 set clk_io_pct 0.2
 set duty_cycle 0.49
 
diff --git a/flow/designs/sky130hd/riscv32i/two_phase_clk_constraint.sdc b/flow/designs/sky130hd/riscv32i/two_phase_clk_constraint.sdc
@@ -2,7 +2,7 @@
 
 current_design riscv
 
-set clk_period 6.36
+set clk_period 6.37
 set clk_io_pct 0.2
 set duty_cycle 0.49
 
