- Update README

- Update two_phase_clk_constraint.sdc
- Create specify_files_for_sdc.tcl
- Update two_phase_clk_synth.tcl
- Update variables.mk

Author: leeway64

README.md

@@ -44,6 +44,20 @@ timeline
     : DRC/LVS check (KLayout)
 ```
 
+## Running ORFS with two-phase clocking with latches
+
+```
+make DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk .DEFAULT_GOAL=place MODE=two_phase_clk | tee orfs.log
+```
+
+## Running static timing analysis
+
+Inside `openroad`, run the following:
+
+```
+source platforms/sky130hd/specify_files_for_sdc.tcl
+```
+
 ## Tool Installation
 
 There are different ways to install and develop OpenROAD and ORFS, which is the best fit depends use-case, experience and personal taste.

flow/designs/sky130hd/gcd/two_phase_clk_constraint.sdc

@@ -2,7 +2,7 @@
 
 current_design gcd
 
-set clk_period [expr 3 * 1.1]
+set clk_period [expr 4 * 1.1]
 set clk_io_pct 0.2
 set duty_cycle 0.4
 

flow/platforms/sky130hd/specify_files_for_sdc.tcl

@@ -0,0 +1,9 @@
+set design gcd
+set base_dir "/OpenROAD-flow-scripts/flow"
+
+read_lib $base_dir/platforms/sky130hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+
+
+read_db $base_dir/results/sky130hd/$design/base/3_place.odb
+#read_spef $base_dir/results/sky130hd/$design/base/6_final.spef
+read_sdc $base_dir/results/sky130hd/$design/base/3_place.sdc

flow/scripts/two_phase_clk_synth.tcl

@@ -142,26 +142,23 @@ techmap -autoproc -map $::env(DFF_TO_LATCH_MAP_FILE)
 opt -noff
 
 
-set dfflibmap_args ""
-foreach cell $::env(DONT_USE_CELLS) {
-  lappend dfflibmap_args -dont_use $cell
-}
-
 # Technology mapping of flip-flops
 # dfflibmap only supports one liberty file
 if { [env_var_exists_and_non_empty DFF_LIB_FILE] } {
-  dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$dfflibmap_args
+  dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$lib_dont_use_args
 } else {
-  dfflibmap -liberty $::env(DONT_USE_SC_LIB) {*}$dfflibmap_args
+  dfflibmap {*}$lib_args {*}$lib_dont_use_args
 }
 opt -noff
 
 # Replace undef values with defined constants
 setundef -zero
 
 
-if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
-  puts "Running basic abc"
+if {
+  ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] &&
+  ![env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
+} {
   log_cmd abc {*}$abc_args
 } else {
   scratchpad -set abc9.script $::env(SCRIPTS_DIR)/abc_speed_gia_only.script
@@ -190,11 +187,14 @@ insbuf -buf {*}$::env(MIN_BUF_CELL_AND_PORTS)
 # Reports
 tee -o $::env(REPORTS_DIR)/synth_check.txt check
 
-tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
+tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$lib_args
 
 # check the design is composed exclusively of target cells, and
 # check for other problems
-if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
+if {
+  ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] &&
+  ![env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
+} {
   check -assert -mapped
 } else {
   # Wrapped operator synthesis leaves around $buf cells which `check -mapped`

flow/scripts/variables.mk

@@ -161,6 +161,8 @@ export WRAP_CFG = $(PLATFORM_DIR)/wrapper.cfg
 export TCLLIBPATH := util/cell-veneer $(TCLLIBPATH)
 
 export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl
+export TWO_PHASE_CLK_SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/two_phase_clk_synth.tcl
+
 export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt
 
 export YOSYS_DEPENDENCIES=$(LIB_FILES) $(WRAPPED_LIBS) $(DFF_LIB_FILE) $(VERILOG_FILES) $(SYNTH_NETLIST_FILES) $(LATCH_MAP_FILE) $(ADDER_MAP_FILE) $(SDC_FILE_CLOCK_PERIOD)