finished liteeth

.gitmodules

@@ -10,3 +10,6 @@
 [submodule "designs/src/NyuziProcessor/dev/repo"]
 	path = designs/src/NyuziProcessor/dev/repo
 	url = https://github.com/jbush001/NyuziProcessor.git
+[submodule "designs/src/liteeth/dev/liteeth"]
+	path = designs/src/liteeth/dev/repo
+	url = https://github.com/enjoy-digital/liteeth.git

designs/asap7/liteeth/liteeth_mac_axi_mii/config.mk

@@ -0,0 +1,28 @@
+export DESIGN_NAME = liteeth_mac_axi_mii
+export DESIGN_RESULTS_NAME = $(DESIGN_NAME)
+export DESIGN_NICKNAME = liteeth
+export PLATFORM    = asap7
+
+export USE_XILINX = 1
+
+-include $(BENCH_DESIGN_HOME)/src/liteeth/verilog.mk
+
+export SDC_FILE      = $(PLATFORM_DESIGN_DIR)/$(DESIGN_NAME)/constraint.sdc
+
+export ADDITIONAL_LEFS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_32w384d_sram.lef \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_32w384d_8wm_sram.lef
+
+export ADDITIONAL_LIBS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_32w384d_sram.lib \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_32w384d_8wm_sram.lib
+
+export GDS_ALLOW_EMPTY=fakeram*
+
+export CORE_UTILIZATION = 40
+
+export PLACE_DENSITY = 0.4
+
+export MACRO_PLACE_HALO = 2 2
+
+export ROUTING_LAYER_ADJUSTMENT = 0.2

designs/asap7/liteeth/liteeth_mac_axi_mii/constraint.sdc

@@ -0,0 +1,15 @@
+current_design liteeth_mac_axi_mii
+
+set clk_name clk
+set clk_port_name sys_clock
+set clk_period 610
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

designs/asap7/liteeth/liteeth_mac_wb_mii/config.mk

@@ -0,0 +1,26 @@
+export DESIGN_NAME = liteeth_mac_wb_mii
+export DESIGN_RESULTS_NAME = $(DESIGN_NAME)
+export DESIGN_NICKNAME = liteeth
+export PLATFORM    = asap7
+
+export USE_XILINX = 1
+
+-include $(BENCH_DESIGN_HOME)/src/liteeth/verilog.mk
+
+export SDC_FILE      = $(PLATFORM_DESIGN_DIR)/$(DESIGN_NAME)/constraint.sdc
+
+export ADDITIONAL_LEFS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_32w384d_sram.lef \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_32w384d_8wm_sram.lef
+
+export ADDITIONAL_LIBS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_32w384d_sram.lib \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_32w384d_8wm_sram.lib
+
+export GDS_ALLOW_EMPTY=fakeram*
+
+export CORE_UTILIZATION = 30
+
+export PLACE_DENSITY = 0.4
+
+export MACRO_PLACE_HALO = 5 5

designs/asap7/liteeth/liteeth_mac_wb_mii/constraint.sdc

@@ -0,0 +1,15 @@
+current_design liteeth_mac_wb_mii
+
+set clk_name clk
+set clk_port_name sys_clock
+set clk_period 1000
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

designs/asap7/liteeth/liteeth_udp_raw_rgmii/config.mk

@@ -0,0 +1,28 @@
+export DESIGN_NAME = liteeth_udp_raw_rgmii
+export DESIGN_RESULTS_NAME = $(DESIGN_NAME)
+export DESIGN_NICKNAME = liteeth
+export PLATFORM    = asap7
+
+export USE_LATTICE = 1
+
+-include $(BENCH_DESIGN_HOME)/src/liteeth/verilog.mk
+
+export SYNTH_HIERARCHICAL = 1
+
+export SDC_FILE      = $(PLATFORM_DESIGN_DIR)/$(DESIGN_NAME)/constraint.sdc
+
+export ADDITIONAL_LEFS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_12w128d_sram.lef \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_64w64d_sram.lef
+
+export ADDITIONAL_LIBS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_12w128d_sram.lib \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_64w64d_sram.lib
+
+export GDS_ALLOW_EMPTY=fakeram*
+
+export CORE_UTILIZATION = 35
+
+export MACRO_PLACE_HALO = 5 5
+
+export PLACE_DENSITY = 0.3

designs/asap7/liteeth/liteeth_udp_raw_rgmii/constraint.sdc

@@ -0,0 +1,15 @@
+current_design liteeth_udp_raw_rgmii
+
+set clk_name clk
+set clk_port_name sys_clock
+set clk_period 590
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

designs/asap7/liteeth/liteeth_udp_stream_rgmii/config.mk

@@ -0,0 +1,26 @@
+export DESIGN_NAME = liteeth_udp_stream_rgmii
+export DESIGN_RESULTS_NAME = $(DESIGN_NAME)
+export DESIGN_NICKNAME = liteeth
+export PLATFORM    = asap7
+
+export USE_XILINX = 1
+
+-include $(BENCH_DESIGN_HOME)/src/liteeth/verilog.mk
+
+export SDC_FILE      = $(PLATFORM_DESIGN_DIR)/$(DESIGN_NAME)/constraint.sdc
+
+export ADDITIONAL_LEFS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_12w128d_sram.lef \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_64w64d_sram.lef
+
+export ADDITIONAL_LIBS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_12w128d_sram.lib \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_64w64d_sram.lib
+
+export GDS_ALLOW_EMPTY=fakeram*
+
+export CORE_UTILIZATION = 35
+
+export PLACE_DENSITY = 0.5
+
+export MACRO_PLACE_HALO = 5 5

designs/asap7/liteeth/liteeth_udp_stream_rgmii/constraint.sdc

@@ -0,0 +1,15 @@
+current_design liteeth_udp_stream_rgmii
+
+set clk_name clk
+set clk_port_name sys_clock
+set clk_period 700
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

designs/asap7/liteeth/liteeth_udp_stream_sgmii/config.mk

@@ -0,0 +1,26 @@
+export DESIGN_NAME = liteeth_udp_stream_sgmii
+export DESIGN_RESULTS_NAME = $(DESIGN_NAME)
+export DESIGN_NICKNAME = liteeth
+export PLATFORM    = asap7
+
+export USE_XILINX = 1
+
+-include $(BENCH_DESIGN_HOME)/src/liteeth/verilog.mk
+
+export SDC_FILE      = $(PLATFORM_DESIGN_DIR)/$(DESIGN_NAME)/constraint.sdc
+
+export ADDITIONAL_LEFS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_64w64d_sram.lef \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_64w1024d_sram.lef
+
+export ADDITIONAL_LIBS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_64w64d_sram.lib \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_64w1024d_sram.lib
+
+export GDS_ALLOW_EMPTY=fakeram*
+
+export CORE_UTILIZATION = 40
+
+export PLACE_DENSITY = 0.3
+
+export MACRO_PLACE_HALO = 5 5

designs/asap7/liteeth/liteeth_udp_stream_sgmii/constraint.sdc

@@ -0,0 +1,15 @@
+current_design liteeth_udp_stream_sgmii
+
+set clk_name clk
+set clk_port_name sys_clock
+set clk_period 1000
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

designs/asap7/liteeth/liteeth_udp_usp_gth_sgmii/config.mk

@@ -0,0 +1,24 @@
+export DESIGN_NAME = liteeth_udp_usp_gth_sgmii
+export DESIGN_RESULTS_NAME = $(DESIGN_NAME)
+export DESIGN_NICKNAME = liteeth
+export PLATFORM    = asap7
+
+export USE_XILINX = 1
+
+-include $(BENCH_DESIGN_HOME)/src/liteeth/verilog.mk
+
+export SDC_FILE      = $(PLATFORM_DESIGN_DIR)/$(DESIGN_NAME)/constraint.sdc
+
+export ADDITIONAL_LEFS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_64w64d_sram.lef \
+  $(PLATFORM_DESIGN_DIR)/sram/lef/fakeram_1rw1r_64w1024d_sram.lef
+
+export ADDITIONAL_LIBS = \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_64w64d_sram.lib \
+  $(PLATFORM_DESIGN_DIR)/sram/lib/fakeram_1rw1r_64w1024d_sram.lib
+
+export GDS_ALLOW_EMPTY=fakeram*
+
+export CORE_UTILIZATION = 35
+
+export PLACE_DENSITY = 0.3

designs/asap7/liteeth/liteeth_udp_usp_gth_sgmii/constraint.sdc

@@ -0,0 +1,15 @@
+current_design liteeth_udp_usp_gth_sgmii
+
+set clk_name clk
+set clk_port_name sys_clock
+set clk_period 1000
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]