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6 changes: 6 additions & 0 deletions .gitignore
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Expand Up @@ -2,6 +2,12 @@
generated/
test_run_dir/*

### Xilinx Vivado files, custom for LSM-Compactron3000
*.gen/
*.hw/
*.cache/
*.ip_user_files/

### XilinxISE template
# intermediate build files
*.bgn
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15 changes: 15 additions & 0 deletions README.md
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Expand Up @@ -81,6 +81,21 @@ The proposed memory sizes are described in the table below.
- [Collection of different useful small Chisel3 projects](https://github.com/j-marjanovic/chisel-stuff)
- [Project that shows how Chisel and Rust can have a custom peripherals](https://github.com/ekiwi/pynq)

- https://github.com/alexforencich/verilog-axi - verilog axi interfaces

- https://github.com/ZipCPU/wb2axip - AXI4, Wishbobe and other interfaces

### Zynq DMA tutorials

- https://www.youtube.com/watch?v=tQpt2N7__NQ
- https://www.youtube.com/watch?v=5gA3xnsSrdo
- https://www.youtube.com/watch?v=Ld01yPmW_Xw
- https://www.youtube.com/watch?v=5MCkjKhn1DM

### Others

- [Version control for Vivado](https://www.fpgadeveloper.com/2014/08/version-control-for-vivado-projects.html/)

## Development

### Create Docker Image
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