merging mips code

Author: v1X3Q0

README.md

@@ -41,7 +41,7 @@ cmake --build build -j8
 In addition to the default build setup, you may want to:
 
 - **Build examples.** To build the [API examples](#examples), pass `-DBN_API_BUILD_EXAMPLES=ON` to CMake when configuring the build. After the build succeeds, you can install the built plugins by running the `install` target. When using the "Unix Makefiles" build generator, this looks like: `make install`.
-- **Build UI plugins.** You will need Qt 6.6.1 (as of writing) installed to build UI plugins.
+- **Build UI plugins.** You will need Qt 6.7.2 (as of writing) installed to build UI plugins.
 - **Build headlessly.** If you are using a headless Binary Ninja distribution or you do not wish to build UI plugins, pass `-DHEADLESS=ON` to CMake when configuring the build.
 
 ### Troubleshooting

arch/arm64/arch_arm64.cpp

@@ -266,6 +266,7 @@ class Arm64Architecture : public Architecture
  protected:
 	size_t m_bits;
 	bool m_onlyDisassembleOnAlignedAddresses;
+	bool m_preferIntrinsics;
 
 	virtual bool Disassemble(const uint8_t* data, uint64_t addr, size_t maxLen, Instruction& result)
 	{
@@ -717,6 +718,7 @@ class Arm64Architecture : public Architecture
 	{
 		Ref<Settings> settings = Settings::Instance();
 		m_onlyDisassembleOnAlignedAddresses = settings->Get<bool>("arch.aarch64.disassembly.alignRequired") ? 1 : 0;
+		m_preferIntrinsics = settings->Get<bool>("arch.aarch64.disassembly.preferIntrinsics") ? 1 : 0;
 	}
 
 	bool CanAssemble() override { return true; }
@@ -1238,7 +1240,15 @@ class Arm64Architecture : public Architecture
 		}
 
 		len = 4;
-		return GetLowLevelILForInstruction(this, addr, il, instr, GetAddressSize(), m_onlyDisassembleOnAlignedAddresses);
+		return GetLowLevelILForInstruction(this, addr, il, instr, GetAddressSize(), m_onlyDisassembleOnAlignedAddresses, [&]() -> bool
+			{
+				Ref<Function> f = il.GetFunction();
+				Ref<BinaryView> v;
+				Ref<Settings> s = Settings::Instance();
+				if (s && f && (v = f->GetView()))
+					return m_preferIntrinsics && s->Get<bool>("arch.aarch64.disassembly.preferIntrinsics", v);
+				return true;
+			});
 	}
 
 
@@ -3513,6 +3523,13 @@ static void InitAarch64Settings()
 			"default" : true,
 			"description" : "Require instructions be on 4-byte aligned addresses to be disassembled."
 			})");
+	settings->RegisterSetting("arch.aarch64.disassembly.preferIntrinsics",
+			R"({
+			"title" : "AARCH64 Prefer Intrinsics for Vector Operations",
+			"type" : "boolean",
+			"default" : true,
+			"description" : "Prefer generating calls to intrinsics (where one is available) to lifting vector operations as unrolled loops (where available). Note that not all vector operations are currently lifted as either intrinsics or unrolled loops."
+			})");
 }
 
 

arch/arm64/arm64test.py

@@ -22944,6 +22944,7 @@ AA87DFC4 orr x4, x30, x7, asr #0x37
 AACAA00F orr x15, x0, x10, ror #0x28
 AADF5572 orr x18, x11, xzr, ror #0x15
 // ORR_asimdimm_L_hl 0x00111100000xxx10x1xxxxxxxxxxxx
+4F04B676 orr v22.8h, #0x93, lsl #0x8
 0F04B676 orr v22.4h, #0x93, lsl #0x8
 0F059527 orr v7.4h, #0xa9
 4F0494CA orr v10.8h, #0x86