Reading:
1. https://www.electronicspecifier.com/attachment/view/5d5fb3495a8ec9e14f8b456d/Xilinx%20VU19P%20Datasheet
2. https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview?homepageId=18844350
3. VIVADO从此开始__高亚军编著.pdf - https://leiblog.wang/static/FPGA/books/Vivado%E4%BB%8E%E6%AD%A4%E5%BC%80%E5%A7%8B/
4. Practical electroics for Inventors

What to expect from an FPGA Engineer
1. https://voltagedivide.com/2023/04/03/growing-as-an-fpga-developer/
2. https://www.reddit.com/r/FPGA/comments/12zs70b/skills_for_fpga_engineer/
3. https://www.reddit.com/r/FPGA/comments/1anl3vi/what_skills_do_you_expect_from_someone_applying/


Bus
PG059 - AXI INTERCONNECT LogiCore IP 
PG373 - AXI Register Slice LogiCore IP


========
Ethernet
========
DS759 - LogiCore IP AXI Ethernet


====
PCIe
====
https://www.amd.com/en/products/adaptive-socs-and-fpgas/technologies/pci-express.html
pg213 - UltraScale+ Devices Integrated Block for PCI Express
pg239 - PCIe Express PHY
PCIe Debug - https://xilinx.github.io/pcie-debug-kmap/pciedebug/build/html/docs/PCIe_Collaterals/PCIe_LFARs_Long_Form_Answer_Records.html

===
DDR
===
UG586 - https://docs.amd.com/r/en-US/ug586_7Series_MIS/Clocking-Architecture?tocId=vKZi3JogyCep57tDVzAT3Q

===================
Gigabit Transceiver
===================
UG578 - https://docs.amd.com/v/u/en-US/ug578-ultrascale-gty-transceivers


Tooling
UG896 - Designing with IP
UG1580 - UpdateMEM User Guide
ICAP

File Extension
.coe (COEfficient)
.mni


Expensive FPGA
**************
https://docs.amd.com/r/en-US/Alveo-X3522PV-Adaptable-Accelerator-Card-User-Guide-UG1607/Introduction


Custom FPGA projects
********************
1. https://github.com/lekgolo167/enxor-logic-analyzer