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initial checkin to add an s32g machine with a53 cores, some memory, arm generic timer, gicv3, and pl011 uart. builds, no attempt to verify whether anything works
Need to disable secure mode or provide memory for the el3 addr space. This change sets a property to disable secure mode. Fix a bug where get_system_memory is called too early and returns null. Now it is called in nxp_s32g_init.
At present we expect struct arm_boot_info::get_dtb() to return the device tree pointer as well as the device tree size. However, this is not necessary as we can get the device tree size via the device tree header directly. Change get_dtb() signature to drop the *size argument, and get the size by ourselves. Signed-off-by: Bin Meng <[email protected]>
By default QEMU generates a 1 MiB sized device tree. Let's pack it to save some room. Signed-off-by: Bin Meng <[email protected]>
Initially, this machine was implemented with physical memory starting at address 0x0. This is not faithful to the real platform, so change it to 0x80000000 to match. Signed-off-by: Nelson Ho <[email protected]>
This change adds a timer node to the device tree with interrupt mappings for the arm generic timer. Add required top level interrupt-parent property to the generated device tree. Change default psci conduit from HVC to SMC. Signed-off-by: Nelson Ho <[email protected]>
Initially, I had set the gic redist size to 0x80000. Each cpu needs 2 frames of 0x10000 each, so 0x80000 is only enough to support 4 cpus. If the redist size is too small, then during secondary CPU initialization we try to access an unmapped address and cause a data abort to be generated. Signed-off-by: Nelson Ho <[email protected]>
This change adds a new virtual device implementation attempting to emulate the NXP/Freescale LINFlexD, but currently only implements the device's UART mode. This change also replaces the PL011 device used in the NXP S32G machine model with the new LINFlex serial device. Signed-off-by: Nelson Ho <[email protected]>
Fix the following build error when compiling fsl-linflex.c: error: ‘r’ may be used uninitialized in this function [-Werror=maybe-uninitialized] Signed-off-by: Bin Meng <[email protected]>
The status register bits are W1C hence the new value after written should have the pending status bits cleared. Signed-off-by: Bin Meng <[email protected]>
Handle W1C bit fields in all implemented registers. Handle read only bits in all implemented registers. Add logging for unimplemented registers Clean up unused defines Reformat some bit field constants Signed-off-by: Nelson Ho <[email protected]>
Create 4 mmio virtio transports for the S32G machine. These will be used to attach virtio-net device. The interrupt map I derived from the virtio device tree node found in the s32g bsp in the vxworks source tree. Signed-off-by: Nelson Ho <[email protected]>
This change adds a VMStateDescription structure to this device implementation, which is registered with the Linflex Device Class, and indicates which of the fields within the FslLinflexState structure need to be saved as part of migration. This fixes the snapshot issue on nxp-s32g machine. Signed-off-by: Nelson Ho <[email protected]>
The core count per CPU is also a #define now. JIRA: RHONE-86
Define basic data structures and registers used by vxworks flexcan driver initialization. Signed-off-by: Nelson Ho <[email protected]>
Define init and class init functions for the flexcan device. Implement rudimentary realize function that initializes the mmio space. Implement simple reset function to zero all regs. Define the VMState structure so regs are saved during migration. Declare CanBusState and CanBusClientState members of the flexcan state structure to later be used to interface with the virtual CAN bus. Signed-off-by: Nelson Ho <[email protected]>
This change fixes an issue in the S32G machine implementation where we have member of type PL011State in NxpS32gState stucture, but realizing and accessing the device as type FSL Linflex device. Change the type of the uart member in struct NxpS32gState to Linflex.
QEMU expects to be able to cast the device state structure to a higher abstraction level type (DEVICE, SYS_BUS_DEVICE, etc). As a result, the first member of the device state structure must be a compatible type.
This change adds the needed structures to use RegisterInfo and related helpers to manage register modification and reset. With this change, the flexCAN device has enough functionality that VxWorks can successfully attach the flexCAN driver, and it thinks it as successfully initialized the controller. Signed-off-by: Nelson Ho <[email protected]>
The fsl-linflex serial device can sometimes miss raising an interrupt, resulting in delayed read from vxworks until the next interrupt (when another key is pressed). This results in the device seemingly always being 1 keystroke behind. This change updates the irq status on all writes to the device, instead of only for specific registers. Signed-off-by: Nelson Ho <[email protected]>
Attempting (again) to fix the issue with serial device misbehaving after machine has been booted for some time. This change removes the irq update on register read. This seems to have resolved the issue with the missing (or extra?) interrupt. Copy pasting into the uart termianl still triggers this behavior. Signed-off-by: Nelson Ho <[email protected]>
This change adds emulation of the FRZ/FRZACK bits in the MCR. Also fixes behavior of LPMACK bit when MDIS is asserted. Improves behavior of soft reset bit by resetting all fields of MCR except for the MDIS bit. Signed-off-by: Nelson Ho <[email protected]>
Rename flexcanbus property to canbus so that command line property to specify when attaching canbus to device can be specified as "canbus" instead of "flexcanbus". Signed-off-by: Nelson Ho <[email protected]>
This change renames the system default clock to ipg and creates another clock, per, to use as input for the CAN controller. This change is needed by vxworks, since vxworks flexcan driver specifically looks for "per" clock node in the device tree, instead of looking for the clock phandle specified in the flexcan dt node. Signed-off-by: Nelson Ho <[email protected]>
This change refactors fsl_flexcan.c to model the devices mmio space more accurately. Previously we modeled the entire mmio space as registers, but this was inaccurate since only the first 128 bytes of the device mmio space is backed by registers. The remaining space is backed by embedded ram. After this change, the first 128 bytes of device mmio space is modeled as registers, and the remaining is modeled using generic mmio. This change also includes some preparation work for implementing the message buffers used during transmit and receive. Since these buffers are memory mapped ram on the real device, we refrain from modeling these message buffers as registers. Signed-off-by: Nelson Ho <[email protected]>
This change adds the flexcan controller device to the nxp-s32g machine. Signed-off-by: Nelson Ho <[email protected]>
A bug was introduced in my previous commit to split the flexcan mmio space into two memory regions, one modeling 32 bit registers and the other modeling memory mapped embedded ram, resulting in the register mmio region to be (re)initialized as generic mmio instead of RegisterInfo. This change fixes this issue. Signed-off-by: Nelson Ho <[email protected]>
This change fixes an error in the call to sysbus_connect_irq during flexcan realize in nxp-s32g machine implementation. The device has 4 irq lines, and the gpio index is 0 for each qemu_irq. Signed-off-by: Nelson Ho <[email protected]>
The backing array for the message buffer mmio region was originally allocated as a uint8 array instead of uint32 because the message buffer is implemented as memory mapped embedded RAM, and not registers. However, accesses and fields within the Message Buffer space is aligned to 32 bits. To make parsing the fields from the MB control registers easier down the line, change the backing array to uint32_t so we access MB at 4 byte alignment. Signed-off-by: Nelson Ho <[email protected]>
This change implements transmit functionality for the FlexCAN controller for non-FD CAN frames. It is by no means complete, but it is enough to satisfy the VxWorks driver. Future changes will implement non-FD RX, CANFD TX, and CANFD RX. Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Create the ITS device as part of versal soc and map it into the versal APU memory region. Signed-off-by: Nelson Ho <[email protected]>
Create GIC ITS device tree subnode when creating GIC node. Add msi-map property to pcie controller node. Signed-off-by: Nelson Ho <[email protected]>
size-cells property is not inherited from ancestors in the device tree, so must be explicitly defined in the GIC node. Devices that specify the GIC as the interrupt parent format the size field in their reg property according to the value of the GIC size-cells property. Without the size-cells property in the GIC node, the reg property of the pcie controller and other devices using the GIC as the interrupt parent may be parsed incorrectly, resulting in mmio regions being mapped incorrectly. Signed-off-by: Nelson Ho <[email protected]>
Enable Locality-specific Peripheral Interrupts. Connect the GICv3 to fpd.apu.mr as dma_as for MSI support. The ITS translation tables are stored in memory and the ITS will manage these tables as part of its operation. Signed-off-by: Nelson Ho <[email protected]>
VxWorks does only one pass over the device tree and treats the GIC the same as any other peripheral in terms of initialization priority. As a result, any devices that use dynamic interrupts that specify the GIC as the interrupt parent need to be parsed and initialized after the GIC. To accomodate the VxWorks behavior, place the GIC node in the device tree such that it precedes any other peripherals. Note: Devices that use static interrupts (PPI/SPI) do not have the same requirement, as VxWorks has a mechanism to defer connection of statically assigned interrupts to the interrupt initialization finalize routine. See vxbIntDeferFinalize() Signed-off-by: Nelson Ho <[email protected]>
VxWorks 25.03 updated all references to versal from xilinx versal to amd versal. As a result the old xlnx,versal compat string no longer matches the vxworks board descriptor source. Add the compatible string for amd,versal to the generated dtb so vxworks 25.03 can boot. Signed-off-by: Nelson Ho <[email protected]>
Remove DEFINE_PROP_END_OF_LIST from property arrays and make Property array const per latest conventions. hw/arm/smmu500.c hw/char/fsl-linflex.c hw/misc/xlnx-versal-intlpd-config.c hw/net/can/fsl_flexcan.c Signed-off-by: Nelson Ho <[email protected]>
Upstream renamed sysemu/ directory to system/ Update header include paths in the following: hw/arm/nxp-s32g.c hw/arm/smmu500.c hw/arm/wr-arm.c Signed-off-by: Nelson Ho <[email protected]>
GPEX_NUM_IRQS definition was removed in the upstream to allow machines that integrate GPEX to support more than 4 legacy IRQs. See Alexander Graf's change: hw/pci-host/gpex: Allow more than 4 legacy IRQs In the case of versal-virt machine, use PCI_NUM_PINS instead of GPEX_NUM_IRQS when connecting irqs to GPEX instance. This results in no change since PCI_NUM_PINS is still 4. See num-irqs property in pci-host/gpex.c to specify support for more than 4 legacy IRQ lines when instantiating the GPEX. Signed-off-by: Nelson Ho <[email protected]>
The memory map for imx8mp-evk is defined in the fsl-imx8mp.c source file. To build the device tree, we need to reference the address map from the imx8mp-evk source. Signed-off-by: Nelson Ho <[email protected]>
Create struct Imx8mpEvk to track machine state, with FslImx8mpState soc as a member of Imx8mpEvk machine. Signed-off-by: Nelson Ho <[email protected]>
Create a device tree for imx8mp-evk machine. This change only allocates a new device tree and creates the device tree header. Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Signed-off-by: Nelson Ho <[email protected]>
Change ccm clock-cells property from 0 to 1. This means that any devices that specify the ccm as clock input need to provide a (clk_phandle, clk_specifier) as the value to the clocks property. This change is kind of a mess, since we don't have a good understanding of what the different clock specifiers mean to the hardware. But the VxWorks ccm and enet drivers are not happy unless we provide the clock specifier for all clock inputs. Signed-off-by: Nelson Ho <[email protected]>
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