@@ -73,7 +73,7 @@ localparam reg [3:0] PARITY_REMANENCE_TIMEOUT_WAIT_STATE = 8;
7373localparam reg [3 :0 ] STOP_BITS_EXCHANGE_STATE = 9 ;
7474localparam reg [3 :0 ] SYNCH_STOP_EXCHANGE_STATE = 10 ;
7575
76- localparam reg [31 :0 ] PARITY_ANALYZE_OFFSET = 16 ;
76+ localparam reg [31 :0 ] PARITY_ANALYZE_OFFSET = 64 ;
7777
7878reg [31 :0 ] TICKS_PER_UART_BIT; // = CLK_FREQ / DEFAULT_BAUD_RATE;
7979reg [31 :0 ] HALF_TICKS_PER_UART_BIT; // = TICKS_PER_UART_BIT / 2;
@@ -92,13 +92,14 @@ reg [31:0] rx_bit_counter;
9292// reg [31:0] rx_stop_bit_counter_limit;
9393reg [31 :0 ] rx_timeout;
9494reg [3 :0 ] rx_data_bit_counter;
95- reg rx_data_parity ;
95+ reg [ 3 : 0 ] rx_parity_counter ;
9696integer i;
9797integer j;
9898
9999supply1 vcc;
100100supply0 gnd;
101101
102+
102103fifo #(.FIFO_SIZE(DEFAULT_RECV_BUFFER_LEN), .DATA_WIDTH(DEFAULT_BYTE_LEN))
103104rx_data_buffer (.clk(clk), .clear(rst), .push(rx_byte_received), .pop(rx_read),
104105 .in_data(rx_buffer), .out_data(rx_data), .pushed_last(rx_data_buffer_full));
@@ -118,13 +119,13 @@ begin
118119 rx_bit_counter <= 0 ;
119120 // rx_stop_bit_counter_limit <= 0;
120121 rx_data_bit_counter <= 0 ;
121- rx_data_parity <= 1'b0 ;
122122 rx_err <= 1'b0 ;
123123 TICKS_PER_UART_BIT <= CLK_TICKS_PER_RS232_BIT;
124124 HALF_TICKS_PER_UART_BIT <= CLK_TICKS_PER_RS232_BIT / 2 ;
125125 j <= 0 ;
126126 TOTAL_RX_TIMEOUT <= 6400 ; // ~ 9600 bit/s
127127 rx_timeout <= 0 ;
128+ rx_parity_counter <= 4'b0000 ;
128129 end
129130 else
130131 begin
@@ -142,6 +143,7 @@ begin
142143 begin
143144 rx_state <= SYNCH_WAIT_EXCHANGE_STATE;
144145 cts <= 1'b0 ;
146+ rx_parity_counter <= 4'b0000 ;
145147 end
146148 SYNCH_WAIT_EXCHANGE_STATE:
147149 begin
@@ -187,6 +189,7 @@ begin
187189 rx_state <= DATA_BITS_EXCHANGE_STATE;
188190 rx_bit_counter <= 0 ;
189191 rx_data_bit_counter <= 0 ;
192+ rx_parity_counter <= 4'b0000 ;
190193 end
191194 end
192195 DATA_BITS_EXCHANGE_STATE:
@@ -206,6 +209,8 @@ begin
206209 if (rx_bit_counter == TICKS_PER_UART_BIT - 64 ) // ensure that we read corrected bit value quite away from boards
207210 begin
208211 rx_buffer[rx_data_bit_counter] <= rx;
212+ if (rx == 1'b1 )
213+ rx_parity_counter <= rx_parity_counter + 4'b0001 ;
209214 end
210215
211216 if (rx_bit_counter == TICKS_PER_UART_BIT)
@@ -245,11 +250,6 @@ begin
245250 default :
246251 begin
247252 // using XOR in we have even value of 1, rx_data_parity is 1, otherwise - 0.
248- rx_data_parity <= rx_buffer[0 ];
249- for (j = 1 ; j < DEFAULT_BYTE_LEN; j = j + 1 )
250- begin
251- rx_data_parity <= rx_data_parity ^ rx_buffer[j];
252- end
253253 rx_state <= PARITY_BIT_ANALYZE_STATE;
254254 end
255255 endcase
@@ -259,16 +259,36 @@ begin
259259 begin
260260 if (DEFAULT_PARITY == `EVEN_PARITY)
261261 begin
262- if (rx_data_parity != rx)
262+ if (rx_parity_counter[ 0 ] == 1'b1 ) // odd 1 counter
263263 begin
264- rx_err <= 1'b1 ; // 1
264+ if (rx == 1'b1 )
265+ rx_err <= 1'b0 ;
266+ else
267+ rx_err <= 1'b1 ;
268+ end
269+ else // even 1 counter
270+ begin
271+ if (rx == 1'b0 )
272+ rx_err <= 1'b0 ;
273+ else
274+ rx_err <= 1'b1 ;
265275 end
266276 end
267277 else
268278 begin
269- if (rx_data_parity != ~ rx)
279+ if (rx_parity_counter[ 0 ] == 1'b1 ) // odd 1 counter
270280 begin
271- rx_err <= 1'b1 ; // 1
281+ if (rx == 1'b0 )
282+ rx_err <= 1'b0 ;
283+ else
284+ rx_err <= 1'b1 ;
285+ end
286+ else // even 1 counter
287+ begin
288+ if (rx == 1'b1 )
289+ rx_err <= 1'b0 ;
290+ else
291+ rx_err <= 1'b1 ;
272292 end
273293 end
274294 rx_state <= PARITY_REMANENCE_TIMEOUT_WAIT_STATE;
0 commit comments