Skip to content

Experimental design to bump SPI speed to 25MHz #34

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
zmetzing wants to merge 5 commits into
base: main
Choose a base branch
from
Open

Experimental design to bump SPI speed to 25MHz #34

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
424c7f8
Experimental design to bump SPI speed to 25MHz
zmetzing Dec 31, 2024
dd8efa0
Fixed slow clock freq and duty cycle (now 50%)
zmetzing Dec 31, 2024
f2620a7
Registered clock gating, other changes. Buildable under 2024.2, but n…
zmetzing Jan 3, 2025
561d134
Merge remote-tracking branch 'origin/main' into 25MHz_test
zmetzing Jan 8, 2025
03ec133
Re-generated palette and sprite RAMs
zmetzing Jan 9, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions fpga/.gitignore
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,3 +10,4 @@ vera_module_tcr.dir/
*.xml
*.vcd
*.bak
promote.pfl
78 changes: 75 additions & 3 deletions fpga/source/generated/palette_ram/constraints/palette_ram.ldc
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,7 +1,13 @@
set device "iCE40UP5K"
set speed "High-Performance_1.2V"
set architecture "iCE40UP"
set device_int "itpa08"
set package "SG48"
set package_int "SG48"
set speed "High-Performance_1.2V"
set speed_int "6"
set operation "Industrial"
set family "iCE40UP"
set architecture "ice40tp"
set partnumber "iCE40UP5K-SG48I"
set WRAPPER_INST "lscc_ram_dp_inst"
set FAMILY "iCE40UP"
set MEM_ID "palette_ram"
Expand All @@ -17,10 +23,12 @@ set OUTPUT_CLK_EN 0
set RESETMODE "sync"
set BYTE_ENABLE 1
set BYTE_WIDTH 2
set BYTE_SIZE 8
set ECC_ENABLE 0
set INIT_MODE "mem_file"
set INIT_FILE "misc/palette_ram_palette_ram_copy.mem"
set INIT_FILE "/home/zmetzing/vera-module-local/fpga/source/generated/palette_ram/misc/palette_ram_palette_ram_copy.mem"
set INIT_FILE_FORMAT "hex"
set INIT_DATA_TYPE 1
set INIT_VALUE_00 "0x0BBB008F0AF6077703330F7706400D850EE7000A00C50C4C0AFE08000FFF0000"
set INIT_VALUE_01 "0x0FFF0EEE0DDD0CCC0BBB0AAA0999088807770666055504440333022201110000"
set INIT_VALUE_02 "0x041102000F770C660A5508440633042202110FBB0C990A880866064404330211"
Expand Down Expand Up @@ -85,5 +93,69 @@ set INIT_VALUE_3C "0x00000000000000000000000000000000000000000000000000000000000
set INIT_VALUE_3D "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_3E "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_3F "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_40 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_41 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_42 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_43 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_44 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_45 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_46 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_47 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_48 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_49 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_4A "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_4B "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_4C "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_4D "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_4E "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_4F "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_50 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_51 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_52 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_53 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_54 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_55 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_56 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_57 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_58 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_59 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_5A "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_5B "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_5C "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_5D "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_5E "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_5F "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_60 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_61 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_62 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_63 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_64 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_65 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_66 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_67 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_68 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_69 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_6A "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_6B "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_6C "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_6D "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_6E "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_6F "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_70 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_71 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_72 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_73 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_74 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_75 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_76 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_77 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_78 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_79 "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_7A "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_7B "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_7C "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_7D "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_7E "0x0000000000000000000000000000000000000000000000000000000000000000"
set INIT_VALUE_7F "0x0000000000000000000000000000000000000000000000000000000000000000"


18 changes: 9 additions & 9 deletions fpga/source/generated/palette_ram/palette_ram.cfg
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
{
"INIT_FILE_FORMAT": "hex",
"INIT_FILE": "source/palette_ram.mem",
"REGMODE": false,
"BYTE_ENABLE": true,
"RDATA_WIDTH": 16,
"WDATA_WIDTH": 16,
"RADDR_DEPTH": 256,
"INIT_MODE": "mem_file",
"WADDR_DEPTH": 256
"WADDR_DEPTH": 256,
"WDATA_WIDTH": 16,
"RADDR_DEPTH": 256,
"RDATA_WIDTH": 16,
"REGMODE": false,
"BYTE_ENABLE": true,
"INIT_MODE": "mem_file",
"INIT_FILE": "source/palette_ram.mem",
"INIT_FILE_FORMAT": "hex"
}
27 changes: 15 additions & 12 deletions fpga/source/generated/palette_ram/palette_ram.ipx
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,16 +1,19 @@
<?xml version="1.0" ?>
<RadiantModule architecture="iCE40UP" date="2020 04 15 20:30:32" device="iCE40UP5K" generator="ipgen" library="module" module="ram_dp" name="palette_ram" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.1.0">
<RadiantModule architecture="ice40tp" date="2025 01 08 20:20:09" device="iCE40UP5K" device_int="itpa08" display_module="RAM_DP" display_vendor="latticesemi.com" family="iCE40UP" gen_platform="Radiant" gen_platform_version="2024.2.0.3.0" generator="ipgen" library="module" module="ram_dp" name="palette_ram" operation="Industrial" package="SG48" package_int="SG48" partnumber="iCE40UP5K-SG48I" source_format="Verilog" speed="High-Performance_1.2V" speed_int="6" vendor="latticesemi.com" version="2.4.0">
<Package>
<File modified="2020 04 15 20:30:31" name="design.xml" type="IP-XACT_design"/>
<File modified="2020 04 15 20:30:31" name="rtl/palette_ram_bb.v" type="black_box_verilog"/>
<File modified="2020 04 15 20:30:31" name="testbench/dut_params.v" type="dependency_file"/>
<File modified="2020 04 15 20:30:31" name="misc/palette_ram_tmpl.vhd" type="template_vhdl"/>
<File modified="2020 04 15 20:30:31" name="testbench/dut_inst.v" type="dependency_file"/>
<File modified="2020 04 15 20:30:31" name="misc/palette_ram_tmpl.v" type="template_verilog"/>
<File modified="2020 04 15 20:30:32" name="component.xml" type="IP-XACT_component"/>
<File modified="2020 04 15 20:30:31" name="constraints/palette_ram.ldc" type="timing_constraints"/>
<File modified="2020 04 15 20:30:31" name="palette_ram.cfg" type="cfg"/>
<File modified="2020 04 15 20:30:31" name="rtl/palette_ram.v" type="top_level_verilog"/>
<File modified="2019 09 03 22:49:53" name="testbench/tb_top.v" type="testbench_verilog"/>
<File modified="2025 01 08 20:20:09" name="rtl/palette_ram_bb.v" type="black_box_verilog"/>
<File modified="2025 01 08 20:20:09" name="palette_ram.cfg" type="cfg"/>
<File modified="2025 01 08 20:20:09" name="misc/palette_ram_tmpl.v" type="template_verilog"/>
<File modified="2025 01 08 20:20:09" name="misc/palette_ram_tmpl.vhd" type="template_vhdl"/>
<File modified="2025 01 08 20:20:09" name="rtl/palette_ram.v" type="top_level_verilog"/>
<File modified="2025 01 08 20:20:09" name="constraints/palette_ram.ldc" type="timing_constraints"/>
<File modified="2025 01 08 20:20:09" name="testbench/dut_params.v" type="dependency_file"/>
<File modified="2025 01 08 20:20:09" name="testbench/dut_inst.v" type="dependency_file"/>
<File modified="2025 01 08 20:20:09" name="component.xml" type="IP-XACT_component"/>
<File modified="2025 01 08 20:20:09" name="design.xml" type="IP-XACT_design"/>
<File modified="2021 03 15 23:05:38" name="testbench/mem_model.v" type="testbench_verilog"/>
<File modified="2021 03 15 23:05:36" name="testbench/clk_rst_gen.v" type="testbench_verilog"/>
<File modified="2024 04 10 15:27:42" name="testbench/tb_top.v" type="testbench_verilog"/>
<File modified="2024 04 10 15:27:38" name="testbench/pdp_master.v" type="testbench_verilog"/>
</Package>
</RadiantModule>
Loading