Skip to content

Conversation

@irmen
Copy link
Contributor

@irmen irmen commented Jan 2, 2026

The emulator doesn't correctly set the layer y position with relating to VSTOP changes done in line irqs halfway through the screen. Found when the following test program didn't work correctly on emulator but worked fine on hardware:

split.zip

The goal of this program is to "split open" the screen from the middle and scroll the upper part upwards and the lower part downwards. In the emulator, the layer y scroll of the lower part is not updated correctly and the effect is shown wrong (the text is not "pushed down").

note: morphinejh also found another difference in the relevant code in the emulator when compared to the Vera FPGA code where the check against VSTART seemed to be 1 off. (>= vs >) this has been changed as well.

Solution from this PR as discussed on discord: https://discord.com/channels/547559626024157184/1029612422807433269/1455760243442188373

note2: Box16 also exhibits incorrect behavior here, It is unclear to me how this solution must be ported to it because the rendering code seems to be different than in the official emulator...

@morphinejh
Copy link

The VERA code mentioned can be found in composer.v , r48.0.1.

Further, I went back found something else that was impacted and needs changed:
Issue - Original Solution

New solution:
Line ~1159: if ( y < vstart || y >= (vstop-1) ) {

@irmen
Copy link
Contributor Author

irmen commented Jan 4, 2026

New solution: Line ~1159: if ( y < vstart || y >= (vstop-1) ) {

@morphinejh hmmm, is this correct? This will make a difference of 2 scan lines compared to the old situation, that seems much?

@morphinejh
Copy link

New solution: Line ~1159: if ( y < vstart || y >= (vstop-1) ) {

@morphinejh hmmm, is this correct? This will make a difference of 2 scan lines compared to the old situation, that seems much?

If the changes are added to match the VERA, the 'fix' for the issue identified in the link comes back without that change as well. At least from my testing.

I think this is because the VERA doesn't inspect the lower bit of VSTOP. So VSTOP is always a multiple of 2.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants