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New Tutorial: AIE/D/14-Bitonic-sorting
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‎AI_Engine_Development/AIE/Design_Tutorials/14-Bitonic-Sorting/Makefile‎

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#
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# Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
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# SPDX-License-Identifier: MIT
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#
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# Author: Mark Rollins
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ECHO = @echo
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export TARGET := hw
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RELEASE=2023.2
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BOARD=vck190
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BASE_NUM=202320_1
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# Platform Selection...
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VERSAL_VITIS_PLATFORM = xilinx_${BOARD}\_base_${BASE_NUM}
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VITIS_PLATFORM_DIR = ${PLATFORM_REPO_PATHS}/${VERSAL_VITIS_PLATFORM}
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export VITIS_PLATFORM_XPFM = ${VITIS_PLATFORM_DIR}/${VERSAL_VITIS_PLATFORM}.xpfm
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# Set SysRoot, RootFS and Image
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export VITIS_SYSROOTS = ${COMMON_IMAGE_VERSAL}/sysroots/cortexa72-cortexa53-xilinx-linux
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export SDKTARGETSYSROOT = ${VITIS_SYSROOTS}
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export KERNEL_IMAGE = ${COMMON_IMAGE_VERSAL}/Image
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export ROOTFS = ${COMMON_IMAGE_VERSAL}/rootfs.ext4
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export XLNX_VERSAL = ${COMMON_IMAGE_VERSAL}
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export PLATFORM = ${VITIS_PLATFORM_XPFM}
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export SYSROOT = ${SDKTARGETSYSROOT}
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##############
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# Build Flow #
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##############
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.PHONY: clean help
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help::
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$(ECHO) "Makefile Usage:"
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$(ECHO) " make all"
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$(ECHO) " Command to compile and simulate all designs"
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$(ECHO) ""
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$(ECHO) " make clean"
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$(ECHO) " Command to remove all the generated files."
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all: all_fft
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all_fft:
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$(MAKE) all -C bitonic_fp16
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$(MAKE) all -C bitonic_fp1024
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$(MAKE) all -C sortcpp_fp16
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$(MAKE) all -C sortcpp_fp1024
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clean:
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$(MAKE) clean -C bitonic_fp16
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$(MAKE) clean -C bitonic_fp1024
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$(MAKE) clean -C sortcpp_fp16
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$(MAKE) clean -C sortcpp_fp1024
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@/bin/rm -rf .crashReporter*
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‎AI_Engine_Development/AIE/Design_Tutorials/14-Bitonic-Sorting/README.md‎

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‎AI_Engine_Development/AIE/Design_Tutorials/14-Bitonic-Sorting/bitonic_fp1024/Makefile‎

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#
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# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
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# SPDX-License-Identifier: MIT
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#
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# Author: Mark Rollins
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AIE_SIM_ONLY := false
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SIM_FIFO := false
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MY_APP := bitonic_fp1024_app
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MY_SOURCES := ${MY_APP}.cpp bitonic_fp1024.h bitonic_fp1024.cpp bitonic_fp1024_graph.h
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PLATFORM_USE := xilinx_vck190_base_202320_1
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PLATFORM ?= ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
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CHECK_FIFO := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing
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AIE_OUTPUT := libadf.a
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AIE_FLAGS := --platform=${PLATFORM} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
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ifeq (${SIM_FIFO}, true)
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AIE_FLAGS := ${AIE_FLAGS} ${CHECK_FIFO}
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endif
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ifeq (${AIE_SIM_ONLY},true)
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AIE_FLAGS := ${AIE_FLAGS} --aie.Xpreproc="-DAIE_SIM_ONLY"
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endif
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.PHONY: help clean x86com x86sim sim profile throughput
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help::
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@echo "Makefile Usage:"
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@echo " make all"
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@echo " Command to generate everything for this design"
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@echo ""
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@echo " make compile"
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@echo " Run AIE compiler and build the design"
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@echo ""
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@echo " make profile"
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@echo " Run AIE simulator with profiling and generate outputs suitable for Vitis Analyzer"
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@echo ""
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@echo " make analyze"
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@echo " Run Vitis Analyzer to inspect results"
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@echo ""
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@echo " make throughput"
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@echo " Evaluate the achieved throughput at the output"
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@echo ""
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@echo " make clean"
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@echo " Command to remove all the generated files."
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all: ${AIE_OUTPUT} sim
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x86all: clean x86com x86sim
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gen_vectors:
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matlab -batch "gen_vectors"
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${AIE_OUTPUT}: ${MY_SOURCES}
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v++ --compile --config aie.cfg --mode aie --target=hw ${AIE_FLAGS} |& tee log
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x86com:
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v++ --compile --config aie.cfg --mode aie --target=x86sim ${AIE_FLAGS} |& tee log
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sim:
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aiesimulator |& tee -a log
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x86sim:
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x86simulator |& tee -a log
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profile:
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aiesimulator --online -wdb -text --profile |& tee -a log
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trace:
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aiesimulator --online -wdb -text |& tee -a log
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throughput:
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@../../tools/python/throughput.py aiesimulator_output/data/sig_o.txt
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loop_II:
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@../../tools/python/get_loop_II.py Work/aie
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regression:
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matlab -batch regression
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analyze:
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vitis_analyzer aiesimulator_output/default.aierun_summary
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clean:
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rm -rf .Xil Work libadf.a
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rm -rf aiesimulator_output* aiesimulator*.log
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rm -rf x86simulator_output*
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rm -rf log log*
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rm -rf *.xpe *.elf *.db *.soln Map_* xnw* *.lp *.log .xil .Xil *.lp *.db *.log *.exe *.vcd *.json
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rm -rf vitis_analyzer* pl_sample_counts* pl_sample_count_*
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rm -rf temp ISS_RPC_SERVER_PORT .crashReporter .AIE_SIM_CMD_LINE_OPTIONS
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rm -rf system*.* trdata.aiesim function_wdb_dir
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‎AI_Engine_Development/AIE/Design_Tutorials/14-Bitonic-Sorting/bitonic_fp1024/aie.cfg‎

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#
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# Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
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# SPDX-License-Identifier: MIT
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#
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# Author: Mark Rollins
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[aie]
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kernel-linting=true
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xlopt=1
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verbose=true
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pl-freq=625
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Xmapper=BufferOptLevel9

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