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[wip]Extend vector composite register class with fifo registers
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-28
lines changed

3 files changed

+50
-28
lines changed

‎llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp‎

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -684,52 +684,52 @@ void AIE2PInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
684684
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
685685
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
686686
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
687-
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
688-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
687+
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
688+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
689689
getKillRegState(KillSrc));
690690
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
691-
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
692-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
691+
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
692+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
693693
getKillRegState(KillSrc));
694694
} else if ((AIE2P::VEC1024RegClass.contains(SrcReg)) &&
695695
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
696696
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
697-
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
697+
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
698698
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
699699
getKillRegState(KillSrc));
700700
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
701-
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
701+
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
702702
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
703703
getKillRegState(KillSrc));
704704
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
705705
(AIE2P::VEC1024RegClass.contains(DstReg))) {
706706
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
707707
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
708-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
708+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
709709
getKillRegState(KillSrc));
710710
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
711711
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
712-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
712+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
713713
getKillRegState(KillSrc));
714714
} else if ((AIE2P::ACC1024RegClass.contains(SrcReg)) &&
715715
(AIE2P::FIFO1024RegClass.contains(DstReg))) {
716716
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
717-
TRI.getSubReg(DstReg, AIE2P::sub_lo_fifo))
717+
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
718718
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
719719
getKillRegState(KillSrc));
720720
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
721-
TRI.getSubReg(DstReg, AIE2P::sub_hi_fifo))
721+
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
722722
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
723723
getKillRegState(KillSrc));
724724
} else if ((AIE2P::FIFO1024RegClass.contains(SrcReg)) &&
725725
(AIE2P::ACC1024RegClass.contains(DstReg))) {
726726
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
727727
TRI.getSubReg(DstReg, AIE2P::sub_512_lo))
728-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_lo_fifo),
728+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_lo),
729729
getKillRegState(KillSrc));
730730
BuildMI(MBB, MBBI, DL, get(AIE2P::VMOV_alu_mv_mv_x),
731731
TRI.getSubReg(DstReg, AIE2P::sub_512_hi))
732-
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_hi_fifo),
732+
.addReg(TRI.getSubReg(SrcReg, AIE2P::sub_512_hi),
733733
getKillRegState(KillSrc));
734734
} else if ((AIE2P::eLRegClass.contains(SrcReg)) &&
735735
(AIE2P::EXPVEC64RegClass.contains(DstReg))) {
@@ -755,6 +755,7 @@ void AIE2PInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
755755
(AIE2P::ePSRFLdFRegClass.contains(DstReg))) {
756756
copyThroughSubRegs(MBB, MBBI, DL, DstReg, SrcReg, KillSrc);
757757
} else {
758+
LLVM_DEBUG(MBBI->dump(););
758759
llvm_unreachable("unhandled case in copyPhysReg");
759760
}
760761
}
@@ -1066,8 +1067,8 @@ AIE2PInstrInfo::getSpillPseudoExpandInfo(const MachineInstr &MI) const {
10661067
return {{AIE2P::VST_dmx_sts_bm_spill, AIE2P::sub_512_lo},
10671068
{AIE2P::VST_dmx_sts_bm_spill, AIE2P::sub_512_hi}};
10681069
case AIE2P::VST_FIFO_SPILL:
1069-
return {{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_lo_fifo},
1070-
{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_hi_fifo}};
1070+
return {{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_512_lo},
1071+
{AIE2P::VST_dmx_sts_fifohl_spill, AIE2P::sub_512_hi}};
10711072
case AIE2P::VST_PLFR_SPILL:
10721073
return {{AIE2P::VST_FIFO_SPILL, AIE2P::sub_fifo},
10731074
{AIE2P::ST_dms_sts_spill, AIE2P::sub_avail},
@@ -1103,8 +1104,8 @@ AIE2PInstrInfo::getSpillPseudoExpandInfo(const MachineInstr &MI) const {
11031104
return {{AIE2P::VLDA_dmx_lda_bm_spill, AIE2P::sub_512_lo},
11041105
{AIE2P::VLDA_dmx_lda_bm_spill, AIE2P::sub_512_hi}};
11051106
case AIE2P::VLDA_FIFO_SPILL:
1106-
return {{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_lo_fifo},
1107-
{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_hi_fifo}};
1107+
return {{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_512_lo},
1108+
{AIE2P::VLDA_dmx_lda_fifohl_spill, AIE2P::sub_512_hi}};
11081109
case AIE2P::VLDA_PLFR_SPILL:
11091110
return {
11101111
{AIE2P::VLDA_FIFO_SPILL, AIE2P::sub_fifo},

‎llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2461,7 +2461,7 @@ bool AIE2PInstructionSelector::selectWideG_AIE_LOAD_STORE(
24612461
RC1024 = &AIE2P::VEC1024RegClass;
24622462
} else if (RBID == AIE2P::FifoRegBankID) {
24632463
RC512 = &AIE2P::FIFO512RegClass;
2464-
SubRegIdxes = {AIE2P::sub_lo_fifo, AIE2P::sub_hi_fifo};
2464+
SubRegIdxes = {AIE2P::sub_512_lo, AIE2P::sub_512_hi};
24652465
RC1024 = &AIE2P::FIFO1024RegClass;
24662466
} else {
24672467
llvm_unreachable("Unknown Register Bank ID!");

‎llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.td‎

Lines changed: 32 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -275,21 +275,42 @@ class AIE2PDim3DRegisterClass <dag reglist, RegAltNameIndex idx = NoRegAltName>
275275
// Core ID
276276
def CORE_ID : AIE2PSPLReg<10, "core_id">;
277277
def mCoreID : AIE2P20BitRegisterClass<(add CORE_ID)>;
278+
279+
let isArtificial = 1 in {
280+
def dummy_sfh_l : AIE2P3BitReg<0, "dummy_sfh_l">;
281+
def dummy_sfh_h : AIE2P3BitReg<0, "dummy_sfh_h">;
282+
def dummy_sfl_l : AIE2P3BitReg<0, "dummy_sfl_l">;
283+
def dummy_sfl_h : AIE2P3BitReg<0, "dummy_sfl_h">;
284+
285+
def dummy_lfh0_l : AIE2P3BitReg<0, "dummy_lfh0_l">;
286+
def dummy_lfh0_h : AIE2P3BitReg<0, "dummy_lfh0_h">;
287+
def dummy_lfl0_l : AIE2P3BitReg<0, "dummy_lfl0_l">;
288+
def dummy_lfl0_h : AIE2P3BitReg<0, "dummy_lfl0_h">;
289+
290+
def dummy_lfh1_l : AIE2P3BitReg<0, "dummy_lfh1_l">;
291+
def dummy_lfh1_h : AIE2P3BitReg<0, "dummy_lfh1_h">;
292+
def dummy_lfl1_l : AIE2P3BitReg<0, "dummy_lfl1_l">;
293+
def dummy_lfl1_h : AIE2P3BitReg<0, "dummy_lfl1_h">;
294+
}
295+
296+
let SubRegIndices = [sub_256_lo, sub_256_hi], CoveredBySubRegs = 1 in {
278297
// Store FIFO register
279-
def sfh : AIE2P3BitReg<0b110,"sfh">;
280-
def sfl : AIE2P3BitReg<0b011,"sfl">;
298+
def sfh : AIE2P3BitReg<0b110,"sfh", [dummy_sfh_l, dummy_sfh_h]>;
299+
def sfl : AIE2P3BitReg<0b011,"sfl", [dummy_sfl_l, dummy_sfl_h]>;
281300
// Load FIFO register 0
282-
def lfh0 : AIE2P1BitReg<0b0,"lfh0">;
283-
def lfl0 : AIE2P1BitReg<0b0,"lfl0">;
301+
def lfh0 : AIE2P1BitReg<0b0,"lfh0", [dummy_lfh0_l, dummy_lfh0_h]>;
302+
def lfl0 : AIE2P1BitReg<0b0,"lfl0", [dummy_lfl0_l, dummy_lfl0_h]>;
284303
// Load FIFO register 1
285-
def lfh1 : AIE2P1BitReg<0b1,"lfh1">;
286-
def lfl1 : AIE2P1BitReg<0b1,"lfl1">;
304+
def lfh1 : AIE2P1BitReg<0b1,"lfh1", [dummy_lfh1_l, dummy_lfh1_h]>;
305+
def lfl1 : AIE2P1BitReg<0b1,"lfl1", [dummy_lfl1_l, dummy_lfl1_h]>;
306+
}
307+
287308
// Load FIFO extra register
288309
def lfe : AIE2P3BitReg<0b010,"lfe">;
289310

290311
def sub_lo_fifo: SubRegIndex<512, 0>;
291312
def sub_hi_fifo : SubRegIndex<512, 512>;
292-
let SubRegIndices = [sub_lo_fifo, sub_hi_fifo], CoveredBySubRegs = 1 in {
313+
let SubRegIndices = [sub_512_lo, sub_512_hi], CoveredBySubRegs = 1 in {
293314
def lf0 : AIE2P1BitReg<0b0, "lf0", [lfl0, lfh0]>;
294315
def lf1 : AIE2P1BitReg<0b1, "lf1", [lfl1, lfh1]>;
295316
def sf : AIE2P1BitReg<0b1, "sf", [sfl, sfh]>;
@@ -1003,9 +1024,9 @@ def spill_eDN_to_eR : AIE2PScalarRegisterClass<(add eDN, eR)>;
10031024
def spill_eDJ_to_eR : AIE2PScalarRegisterClass<(add eDJ, eR, eDN)>;
10041025
def spill_eDC_to_eR : AIE2PScalarRegisterClass<(add eDC, eR)>;
10051026

1006-
def spill_vec512_to_composite : AIE2PVector512RegisterClass<(add mXm, mBMm)>;
1007-
def spill_vec1024_to_composite : AIE2PVector1024RegisterClass<(add eY, mCMm)>;
1008-
def spill_acc512_to_composite : AIE2PVector512RegisterClass<(add mBMm, mXm)>;
1009-
def spill_acc1024_to_composite : AIE2PVector1024RegisterClass<(add mCMm, eY)>;
1027+
def spill_vec512_to_composite : AIE2PVector512RegisterClass<(add mXm, mBMm, sfh, sfl, lfh0, lfh1, lfl0, lfl1)>;
1028+
def spill_vec1024_to_composite : AIE2PVector1024RegisterClass<(add eY, mCMm, lf0, lf1, sf)>;
1029+
def spill_acc512_to_composite : AIE2PVector512RegisterClass<(add mBMm, mXm, sfh, sfl, lfh0, lfh1, lfl0, lfl1)>;
1030+
def spill_acc1024_to_composite : AIE2PVector1024RegisterClass<(add mCMm, eY, lf0, lf1, sf)>;
10101031

10111032
} // End AIE2P Namespace

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