Skip to content

Commit 2028caf

Browse files
F-StuckmannF-Stuckmann
committed
[AIE2P] instruction pattern VEXT-ZEXT-BCST
1 parent 9cf7338 commit 2028caf

File tree

2 files changed

+20
-23
lines changed

2 files changed

+20
-23
lines changed

‎llvm/lib/Target/AIE/aie2p/AIE2PInstrPatterns.td‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -948,10 +948,10 @@ class ExtBcstSubvecPat<AIE2PInst Inst, ValueType BcstDstTy,
948948
(Inst VEC512:$s0, IdxTy:$idx)>;
949949

950950
// Extract scalar instead of a subvector
951-
class ExtBcstScalarPat<AIE2PInst Inst, ValueType BcstDstTy,
951+
class ExtBcstScalarPat<SDPatternOperator VextrExt, AIE2PInst Inst, ValueType BcstDstTy,
952952
ValueType ScalarDstTy, DAGOperand IdxTy> :
953953
Pat<(BcstDstTy (bcst_vector_node
954-
(ScalarDstTy(vextract_sext(BcstDstTy VEC512:$s0),
954+
(ScalarDstTy(VextrExt(BcstDstTy VEC512:$s0),
955955
(i32 IdxTy:$idx))))),
956956
(Inst VEC512:$s0, IdxTy:$idx)>;
957957

@@ -982,17 +982,20 @@ defset list<ExtBcstPair> ExtBcst64Pairs={
982982
}
983983

984984
foreach Pair = ExtBcst8Pairs in {
985-
def : ExtBcstScalarPat<Pair.Inst, v64i8, i32, Pair.IdxTy>;
985+
def : ExtBcstScalarPat<vextract_sext, Pair.Inst, v64i8, i32, Pair.IdxTy>;
986+
def : ExtBcstScalarPat<vextract_zext, Pair.Inst, v64i8, i32, Pair.IdxTy>;
986987
}
987988

988989
foreach Pair = ExtBcst16Pairs in {
989-
def : ExtBcstScalarPat<Pair.Inst, v32i16, i32, Pair.IdxTy>;
990+
def : ExtBcstScalarPat<vextract_sext, Pair.Inst, v32i16, i32, Pair.IdxTy>;
991+
def : ExtBcstScalarPat<vextract_zext,Pair.Inst, v32i16, i32, Pair.IdxTy>;
990992
}
991993

992994
foreach Pair = ExtBcst32Pairs in {
993995
def : ExtBcstSubvecPat<Pair.Inst, v64i8, v4i8, Pair.IdxTy>;
994996
def : ExtBcstSubvecPat<Pair.Inst, v32i16, v2i16, Pair.IdxTy>;
995-
def : ExtBcstScalarPat<Pair.Inst, v16i32, i32, Pair.IdxTy>;
997+
def : ExtBcstScalarPat<vextract_sext, Pair.Inst, v16i32, i32, Pair.IdxTy>;
998+
def : ExtBcstScalarPat<vextract_zext, Pair.Inst, v16i32, i32, Pair.IdxTy>;
996999
}
9971000

9981001
foreach Pair = ExtBcst64Pairs in {

‎llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-vextbcst.mir‎

Lines changed: 12 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -377,9 +377,8 @@ body: |
377377
; CHECK-NEXT: {{ $}}
378378
; CHECK-NEXT: %ptr:ep = COPY $p0
379379
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<64 x s8>))
380-
; CHECK-NEXT: [[VEXTRACT_8_vec_extract_imm_vaddSign0_:%[0-9]+]]:er = VEXTRACT_8_vec_extract_imm_vaddSign0 [[VLD_x_idx_imm_pseudo]], 0, implicit $vaddsign0
381-
; CHECK-NEXT: [[VBCST_8_:%[0-9]+]]:vec512 = VBCST_8 [[VEXTRACT_8_vec_extract_imm_vaddSign0_]]
382-
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_8_]]
380+
; CHECK-NEXT: [[VEXTBCST_8_vec_extract_broadcast_imm:%[0-9]+]]:vec512 = VEXTBCST_8_vec_extract_broadcast_imm [[VLD_x_idx_imm_pseudo]], 0
381+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VEXTBCST_8_vec_extract_broadcast_imm]]
383382
%ptr:ptrregbank(p0) = COPY $p0
384383
%1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
385384
%2:gprregbank(s32) = G_CONSTANT i32 28
@@ -429,9 +428,8 @@ body: |
429428
; CHECK-NEXT: %ptr:ep = COPY $p0
430429
; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r4
431430
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<64 x s8>))
432-
; CHECK-NEXT: [[VEXTRACT_8_vec_extract_r_vaddSign0_:%[0-9]+]]:er = VEXTRACT_8_vec_extract_r_vaddSign0 [[VLD_x_idx_imm_pseudo]], [[COPY]], implicit $vaddsign0
433-
; CHECK-NEXT: [[VBCST_8_:%[0-9]+]]:vec512 = VBCST_8 [[VEXTRACT_8_vec_extract_r_vaddSign0_]]
434-
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_8_]]
431+
; CHECK-NEXT: [[VEXTBCST_8_vec_extract_broadcast_r:%[0-9]+]]:vec512 = VEXTBCST_8_vec_extract_broadcast_r [[VLD_x_idx_imm_pseudo]], [[COPY]]
432+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VEXTBCST_8_vec_extract_broadcast_r]]
435433
%ptr:ptrregbank(p0) = COPY $p0
436434
%1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
437435
%2:gprregbank(s32) = G_CONSTANT i32 28
@@ -478,9 +476,8 @@ body: |
478476
; CHECK-NEXT: {{ $}}
479477
; CHECK-NEXT: %ptr:ep = COPY $p0
480478
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<32 x s16>))
481-
; CHECK-NEXT: [[VEXTRACT_16_vec_extract_imm_vaddSign0_:%[0-9]+]]:er = VEXTRACT_16_vec_extract_imm_vaddSign0 [[VLD_x_idx_imm_pseudo]], 0, implicit $vaddsign0
482-
; CHECK-NEXT: [[VBCST_16_:%[0-9]+]]:vec512 = VBCST_16 [[VEXTRACT_16_vec_extract_imm_vaddSign0_]]
483-
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_16_]]
479+
; CHECK-NEXT: [[VEXTBCST_16_vec_extract_broadcast_imm:%[0-9]+]]:vec512 = VEXTBCST_16_vec_extract_broadcast_imm [[VLD_x_idx_imm_pseudo]], 0
480+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VEXTBCST_16_vec_extract_broadcast_imm]]
484481
%ptr:ptrregbank(p0) = COPY $p0
485482
%1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
486483
%2:gprregbank(s32) = G_CONSTANT i32 28
@@ -529,9 +526,8 @@ body: |
529526
; CHECK-NEXT: %ptr:ep = COPY $p0
530527
; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r2
531528
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<32 x s16>))
532-
; CHECK-NEXT: [[VEXTRACT_16_vec_extract_r_vaddSign0_:%[0-9]+]]:er = VEXTRACT_16_vec_extract_r_vaddSign0 [[VLD_x_idx_imm_pseudo]], [[COPY]], implicit $vaddsign0
533-
; CHECK-NEXT: [[VBCST_16_:%[0-9]+]]:vec512 = VBCST_16 [[VEXTRACT_16_vec_extract_r_vaddSign0_]]
534-
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_16_]]
529+
; CHECK-NEXT: [[VEXTBCST_16_vec_extract_broadcast_r:%[0-9]+]]:vec512 = VEXTBCST_16_vec_extract_broadcast_r [[VLD_x_idx_imm_pseudo]], [[COPY]]
530+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VEXTBCST_16_vec_extract_broadcast_r]]
535531
%ptr:ptrregbank(p0) = COPY $p0
536532
%1:vregbank(<16 x s32>) = G_IMPLICIT_DEF
537533
%2:gprregbank(s32) = G_CONSTANT i32 28
@@ -576,9 +572,8 @@ body: |
576572
; CHECK-NEXT: {{ $}}
577573
; CHECK-NEXT: %ptr:ep = COPY $p0
578574
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<16 x s32>))
579-
; CHECK-NEXT: [[VEXTRACT_32_vec_extract_imm_vaddSign0_:%[0-9]+]]:er = VEXTRACT_32_vec_extract_imm_vaddSign0 [[VLD_x_idx_imm_pseudo]], 0, implicit $vaddsign0
580-
; CHECK-NEXT: [[VBCST_32_:%[0-9]+]]:vec512 = VBCST_32 [[VEXTRACT_32_vec_extract_imm_vaddSign0_]]
581-
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_32_]]
575+
; CHECK-NEXT: [[VEXTBCST_32_vec_extract_broadcast_imm:%[0-9]+]]:vec512 = VEXTBCST_32_vec_extract_broadcast_imm [[VLD_x_idx_imm_pseudo]], 0
576+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VEXTBCST_32_vec_extract_broadcast_imm]]
582577
%ptr:ptrregbank(p0) = COPY $p0
583578
%4:vregbank(<16 x s32>) = G_LOAD %ptr(p0) :: (load (<16 x s32>))
584579
%483:gprregbank(s32) = G_CONSTANT i32 0
@@ -623,9 +618,8 @@ body: |
623618
; CHECK-NEXT: %ptr:ep = COPY $p0
624619
; CHECK-NEXT: [[VLD_x_idx_imm_pseudo:%[0-9]+]]:vec512 = VLD_x_idx_imm_pseudo %ptr, 0 :: (load (<16 x s32>))
625620
; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r6
626-
; CHECK-NEXT: [[VEXTRACT_32_vec_extract_r_vaddSign0_:%[0-9]+]]:er = VEXTRACT_32_vec_extract_r_vaddSign0 [[VLD_x_idx_imm_pseudo]], [[COPY]], implicit $vaddsign0
627-
; CHECK-NEXT: [[VBCST_32_:%[0-9]+]]:vec512 = VBCST_32 [[VEXTRACT_32_vec_extract_r_vaddSign0_]]
628-
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBCST_32_]]
621+
; CHECK-NEXT: [[VEXTBCST_32_vec_extract_broadcast_r:%[0-9]+]]:vec512 = VEXTBCST_32_vec_extract_broadcast_r [[VLD_x_idx_imm_pseudo]], [[COPY]]
622+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VEXTBCST_32_vec_extract_broadcast_r]]
629623
%ptr:ptrregbank(p0) = COPY $p0
630624
%4:vregbank(<16 x s32>) = G_LOAD %ptr(p0) :: (load (<16 x s32>))
631625
%483:gprregbank(s32) = COPY $r6

0 commit comments

Comments
 (0)